基于MMIC工艺的片上射频LC无源滤波器

设计、制作了几种基于MMIC工艺的片上LC低通/带通滤波器并进行了测试. 测试结果表明,一个3nH的MMIC电感在6.8GHz下品质因数达到13.8,自谐振频率达到15.5GHz;制作的LC低通/带通滤波器的截止频率或中心频率与设计偏差很小,分别为2%和3.3%;低通滤波器在各自通带内的插入损耗小于3dB,带通滤波器在中心频率的插入损耗为7.2dB.     

基于MMIC工艺的片上射频LC无源滤波器

设计、制作了几种基于MMIC工艺的片上LC低通/带通滤波器并进行了测试.测试结果表明,一个3nH的MMIC电感在6.8GHz下品质因数达到13.8.自谐振频率达到15.5GHz;制作的LC低通/带通滤波器的截止频率或中心频率与设计偏差很小,分别为2%和3.3%;低通滤波器在各自通带内的插入损耗小于3dB,带通滤波器在中心频率的插入损耗为7.2dB.     

一种程控滤波器的设计

该系统以单片机为控制核心,结合双二阶环路滤波器的基本原理,使其同时具备低通、高通、带通、带阻滤波器的功能,利用DAC等效为可变电阻,实现了滤波器参数的程控。该系统可通过键盘设置滤波器的种类、截止频率和Q值,低通、高通滤波器截止频率以及带通、带阻滤波器中心．频率可预置范围为100Hz～50kHz,Q值范围为0．5～5。系统采用矩阵键盘和LCD液晶显示,人机交互界面友好。     

一种程控滤波器的设计

该系统以单片机为控制核心,结合双二阶环路滤波器的基本原理,使其同时具备低通、高通、带通、带阻滤波器的功能,利用DAC等效为可变电阻,实现了滤波器参数的程控.该系统可通过键盘设置滤波器的种类、截止频率和Q值,低通、高通滤波器截止频率以及带通、带阻滤波器中心频率可预置范围为100 Hz～50 kHz,Q值范围为0.5～5.系统采用矩阵键盘和LCD液晶显示,人机交互界面友好.     

参数可线性重构的电流模式二阶带通滤波器

针对二阶通用带通滤波器存在特征参数不能线性重构的缺点,提出一种全新的特征参数可线性重构的电流模式二阶带通滤波器设计理论.该调谐滤波器通过调节反馈电流放大器的放大系数可线性重构二阶带通滤波器的截止频率、品质因素等参数,而滤波器的幅频特性保持不变.Spectre仿真结果表明,±1.5V电源电压下,滤波器的中心频率和品质因素在2 GHz内可线性重构.     

基于MAX267的自适应带通滤波器的设计

叙述了用开关电容滤波器MAX267构成二阶自适应带通滤波器的设计.根据驱动信号的频率,运用锁相倍频原理为MAX267提供时钟信号,使其带通滤波中心频率将跟随特征信号频率变化,克服了传统滤波器带通中心频率不易改变的缺点,解决了大功率超声应用中基波信息的提取问题,为频率跟踪和功率控制提供了可靠的信息.实验结果表明,该滤波器较好地实现了自适应带通滤波的功能,能应用于大功率超声设备中.     

基于LTC1068-200的低频带通滤波器设计

在蓄电池性能监测过程中,接收的信号都是比较微弱的低频信号,而且为了得到更多的信息,往往向蓄电池施加多个频率的激励。因此,设计带通滤波器以提高抗干扰能力,而且中心频率要可调。开关电容滤波器可实现低通、高通、带通和带阻滤波功能,而且中心频率可调节,文中采用了LTC1068-200开关电容滤波器集成模块进行电路设计,时钟频率由CD4046锁相环控制。仿真结果表明本文设计的滤波器通带宽度可以达到5 Hz,中心频率从10 Hz到1 kHz可调节,满足实际需要。     

可配置开关电容器滤波器支持PSoC功能

滤波器是一种允许或拒绝一个信号的特定频率通过的器件。三类常见的滤波器是低通滤波器、带通滤波器和高通滤波器。理想的低通滤波器允许某一特定截止频率以下的信号通过,并阻断任何高于该截止频率的信号。     

基于液晶材料的带宽可重构毫米波滤波器

根据液晶材料在毫米波段良好的介电特性和调谐能力,设计了一款基于液晶材料的毫米波带宽可重构宽带带通滤波器。滤波器使用一个高通滤波器和一个低通滤波器级联实现带通效果;在低通部分加载液晶材料,通过调谐液晶材料的等效介电常数改变低通滤波器的响应频率,实现带宽的可重构。仿真结果表明,当调谐液晶介电常数从2.4变化到3.8时,滤波器的高频截止频率从52 GHz下降至48 GHz,相对带宽从84.9%变为78.3%。     

用于千兆以太网基带铜缆接收器均衡的甚高频自适应 连续时间Gm-C 二阶带通滤波器的研究和设计

本文设计了用于千兆以太网基带铜缆接收器均衡的甚高频自适应连续时间Gm-C二阶带通滤波器。基于最陡梯度下降算法，带通滤波器的零点在57－340MHz的频率范围内可以自适应地调节，中心频率为1.278GHz。通过外接电阻伺服环路，滤波器中跨导转换器的跨导值不受工艺偏差和温度变化的影响，采用CSMC－HJ0.6μm CMOS工艺器件模型，用Cadence Spectres仿真器仿真了设计的自适应滤波器电路，仿真结果验证了设计原理和设计的电路。系统的最长学习时间为880个参考时钟周期。     

MOS switched-capacitor analog sampled-data direct-form recursive filters

A new technique enabling the integration of audio frequency filters using standard MOS technology is described. This approach uses ratioed MOS capacitors, MOS amplifiers and switches to realize precision multiplication, summation, and delay functions. With these elements an analog sampled-data direct-form recursive filter, having the general biquadratic transfer function, was integrated in MNOS technology. This filter had a Q=19/spl plusmn/1 without external trimming and it could be electrically programmed into low-pass, bandpass, and high-pass responses. This biquadratic section can be used as a building block for higher order filters. The direct form switched-capacitor offers some useful advantages in comparison to the switched-capacitor integrator approach. These are the rejection of MOS amplifier noise and power supply noise below one-half the sampling rate, less silicon area especially when implementing high Q poles, and potential for multiplexing two or more filters.     

Real-time programmable low power SC bandpass filter

A real-time programmable switched capacitor (SC) second-order bandpass filter is presented. It is based on the voltage inverter switch (VIS) principle using inverse recharging devices. These devices are realized with dynamic amplifiers in order to achieve low power dissipation. The filter contains only grounded or virtually grounded network capacitances and, therefore, it is insensitive to the parasitic capacitances between the bottom plate of the implemented MOS capacitors and the substrate. The circuit offers digital programming capability (two Q factors and three center frequencies) and low power dissipation (185 /spl mu/W at a sampling frequency of 8 kHz and with a power supply voltage of 10 V). The filter has been integrated in CMOS metal-gate technology.     

A multiple sampling, single A/D conversion technique for I/Qdemodulation in CMOS

We have developed a CMOS A/D converter for I/Q demodulation with an analog mirror signal suppression filter in the sampling unit. The circuit directly converts a modulated 30 MHz IF signal to digitized I and Q values in the base band with an accuracy of more than 10 b. The output data rate is 2 MHz and the power consumption is 270 mW. By placing the I/Q split mirror suppression filter on the analog side, we can get a highly integrated system solution for a coherent receiver. The circuit uses multiple sampling, that gives the input values to the filter. The sizes of the sampling capacitors determine the coefficients for the filter multiplications. The sampled charges are then added in order to get the filter additions. This total charge is then converted to digital form in a single conversion. By requiring the filter to block DC, the filter subtraction becomes a part of the active offset reduction using correlated double sampling. Careful layout and very simple circuit solutions make the design possible     

Parallel processing architectures for rank order and stack filters

Many architectures have been proposed for rank order and stack filtering. To achieve additional speedup in these structures requires the use of parallel processing techniques such as pipelining and block processing. Pipelining is well understood but few block architectures have been developed for rank order and stack filtering. Block processing is essential for additional speedup when the original architecture has reached the throughput limits caused by the underlying technology. A trivial block structure simply repeats a single input, single output structure to generate a multiple input, multiple output structure. Therefore the architecture can achieve speedups equal to the number of multiple outputs or the block size. However, unlike linear filters, the rank order and stack filter outputs are calculated using comparisons. It is possible to share these comparisons within the block structure and thus substantially reduce the size of the block structure. The authors introduce a systematic method for applying block processing to rank order filters and stack filters. This method takes advantage of shared comparisons within the block structure to generate a block filter with shared substructures whose complexity is reduced by up to one-third compared to the original filter structure times the block size. Furthermore, block processing is important for the generation of low power designs. A block structure can trade its increased speedup for a throughput equal to the original single output architecture but with a significantly lower power requirement. The power reduction in the trivial block structures is limited by the power supply voltage. They demonstrate how block structures with shared substructures allow them to continue decreasing the power consumption beyond the limit imposed by the supply voltage     

MOS sampled data recursive filters using switched capacitor integrators

A new technique to analog sampled data filtering is presented which can be fully integrated using MOS technology. Advantages of this new approach are reduced circuit complexity, low sensitivity to coefficient variations, and efficient utilization of silicon area. Performance of monolithic low Q(Q=1) and high Q(Q=73) filters are presented which were implemented using NMOS technology. In implementing the high Q filter a new operational amplifier design was used which had a 14-V output range, rms noise voltage of 45 /spl mu/V, an open-loop gain of 6000, and a unity-gain bandwidth of 2 MHz.     

New proposal for a multigigabit/s clock recovery IC based on a standard silicon bipolar technology

A clock recovery IC for optical fibre communication at multigigabit/s is proposed. The clock frequency extracted corresponds to half the bit rate. The 2:1 frequency division is carried out by a double balanced mixer and the frequency selection by an SAW filter. Circuit simulations are based on a standard 2 ?m silicon bipolar technology. The circuit was optimisd at 3.4 Gbit/s for a power consumption of 220 mW with a 1.7 GHz SAW filter (Q = 340). The dynamic clock phase jitter, estimated from circuit simulations, is less than 0.5°. Circuit simulations predict that the operating bit rate may be exended up to 4.5 Gbit/s.     

基于光纤SPM效应级联全光再生器的设计优化

基于高非线性光纤SPM(自相位调制)效应加偏移滤波的全光再生技术,分析了级联再生器在输入脉冲宽度、光纤参数和滤波器带宽一定的情况下,输入信号功率和滤波器偏移量对输入信号幅度抖动和Q值的影响.数值仿真结果表明:优化后的输入信号功率和滤波器偏移量使得级联再生后的信号幅度抖动和寄生脉冲都得到了抑制.第2级再生后的Q值改善值比...     

Low-power CMOS continuous-time filters

A design technique for low-power continuous-time filters using digital CMOS technology is presented. The basic building block is a fully-balanced integrator with its unity-gain frequency determined by a small-signal transconductance and MOSFET gate capacitance. Integrator excess phase shift is reduced using balanced signal paths, and open-loop gain is increased using low-voltage cascode amplifiers. Two-pole bandpass and five-pole lowpass ladder filters have been implemented in a 1.2 μm n-well CMOS process. The lowpass prototypes provided 300 kHz-1000 kHz bias-current-tunable -3 dB bandwidth, 67 dB dynamic range with 1% total harmonic distortion (THD), and 30 μW/pole (300 kHz bandwidth) power dissipation with a 1.5 V supply; the bandpass prototypes had a tunable center frequency of 300 kHz-1000 kHz, Q of 8.5, and power dissipation of 75 μW/pole (525 kHz center frequency) from a 1.5 V supply. The active filter area was 0.1 mm²/pole for both designs     

二波段频率源设计

为了设计一个L波段频率源,使其能够稳定输出,采用锁相倍频电路实现高频信号输出,通过Q3236锁相环芯片实现。利用有源比例积分滤波器实现环路滤波器的设计,给出了滤波器参数计算方法。做了大量关于锁相环电路和环路滤波器电路的实验,反复调试得到电路稳定工作最佳状态。最后给出了样机的测试结果,该频率源具有体积小、低功耗、低相噪及频率稳定性好等优点。     

Design and evaluation of a high-precision, fully tunable OTA-Cbandpass filter implemented in GaAs MESFET technology

A second-order bandpass filter employing the operational transconductance amplifier-capacitor (OTA-C) method and featuring independent tuning of center frequency and Q is described. The filter, which is realized in 0.5-μm GaAs MESFET technology, is intended for use in high-precision, continuous-time (CT) IF bandpass filtering applications requiring both accurate amplitude and group delay responses. The filter center frequency is tunable in the range 12-50 MHz, Q is tunable in the range 4-60, and a transfer function accuracy of the order of 1% is achieved throughout the tuning range. Active area is 1 mm² and static power consumption is 230 mW