A highly linear CMOS Gm-C bandpass filter with on-chipfrequency tuning

A fourteenth-order CMOS transconductance-C (G_m-C) bandpass filter with on-chip automatic frequency tuning is described. By using highly linear G_m-C integrators, the filter achieves 75 dB dynamic range over 700 kHz noise bandwidth. The measured intermodulation distortion (IM3) @ 600 kHz for a 4 V_pp input signal is only -61 dB. On-chip automatic frequency tuning provides more than 300% center frequency range (i.e., 165-505 kHz) of the filter with ±1% frequency accuracy. The 0.7-μm CMOS filter measures 4.8 mm ² and consumes 70 mW from a single 5 V power supply     

A CMOS analog front-end circuit for an FDM-based ADSL system

A CMOS analog front-end circuit for an FDM-based ADSL system is presented. The circuit contains all analog functions including AGC amplifiers, continuous-time band pass filters, ΣΔ AD/DA converters, and digital decimation and interpolation filters. On-chip automatic tuning of the bandpass filters provides more than 300% center frequency range with 1% frequency accuracy. The higher-order ΣΔ AD/DA converters achieve 12-b data conversion at 1.54 Msamples/s with an oversampling ratio of only 32. The 0.7 μm CMOS circuit measures 65 mm² and consumes 1.9 W from a single 5 V power supply     

Low Voltage Micropower Log-Domain Filters

A design technique for low-voltage, micropower continuous-time filters implementing CMOS devices operating in weak inversion is presented. The basic building block is the CMOS log-domain integrator. The effects of the MOS device nonidealities on the integrator are investigated and verified by HSPICE simulations. A 5th-order Chebyshev lowpass ladder filter was designed and simulated. The filter operates with low supply voltage of 1.5 V to achieve a cutoff frequency tunable range of 100 Hz–100 kHz, and it has a power dissipation of 254 nW/pole at the cutoff frequency of 100 kHz. The filter was laid out using the 0.35-m mixed-mode polycide CMOS technology and occupies a die area of 0.04 mm² without the i/o pads     

Low-voltage fully differential switched-current filters

An accurate high-frequency switched-current integrator based on low-voltage fully-differential folded-cascode current copiers is presented. A five-pole lowpass ladder filter has been integrated using a 1.2 μm n-well CMOS process without floating precision linear capacitors. Experimental results show an accurate filter response for sampling frequencies up to 5 MHz. Using a nominal 3.3 V power supply, the measured dynamic range is 66 dB and the power dissipation is 10 mW/pole     

A 1.5-V-100-μW ΔΣ modulator with 12-b dynamic rangeusing the switched-opamp technique

The design and implementation of a very low supply voltage/low power ΔΣ modulator is presented. It is based on the switched-opamp technique, which allows low voltage operation with a standard process and without voltage multiplication. The design methodology is illustrated with a second-order single-loop ΔΣ modulator. The chip is implemented in a 0.7-μm CMOS process with standard threshold voltages. The power supply is 1.5 V and the power dissipation is only 100 μW. The measured dynamic range in the speech bandwidth of 300-3400 Hz is 12 b. The total harmonic distortion (THD) is lower than -72 dB     

A high-frequency fifth order switched-current bilinear ellipticlowpass filter

Design considerations for and measured results of a prototype high-frequency fifth order switched-current bilinear elliptic lowpass filter are presented in this paper. The prototype filter was implemented on a standard 1.2 μm double-metal single-polysilicon CMOS process and occupied a total die area of 1.5 mm². When clocked at 2 MHz, the filter achieved a passband edge of 350 kHz, a stopband edge of 420 kHz, a passband ripple of 0.6 dB and a minimum stopband attenuation of 26 dB. With a single 5 V power supply the filter consumed 28 mW     

Integrated selectivity for narrow-band FM IF systems

An 18th-order all-pole continuous-time bandpass filter for IF (intermediate frequency) filtering purposes has been designed and integrated in a 3-μm CMOS process. Implemented using nine fully balanced, transconductor-capacitor coupled resonators, the filter features a 20-kHz bandwidth at 200-kHz center frequency and 54-dB dynamic range (IM3<-40 dB) and consumes 300 μA from a single 4-V supply. With the use of conventional phase-locked loop techniques for automatic tuning, the accuracy of the filter response is comparable to that of ceramic filters. As expected, the fundamental limitations of such an active implementation compared to a passive realization are noise and distortion     

Design techniques for VHF/UHF high-Q tunable bandpass filters usingsimple CMOS inverter-based transresistance amplifiers

In this paper, CMOS inverter-based wideband transresistance R_m amplifiers are proposed and analyzed. Using the R_m amplifiers, tunable VHF/UHF R_m-C bandpass biquadratic filters can be designed. In these filters, the center frequency f₀ can be post-tuned by adjusting the control voltages of the R_m amplifiers. The pseudodifferential configuration uses the extra inversely connected and self-shorted inverters for Q enhancement. Experimental results have shown that the center frequency f₀ of the single-ended-output R_m-C bandpass biquad is 386 MHz (258 MHz) and Q=1.195 (Q=1.012) for ±2.5 V (±1.5 V) supply voltage. The power consumption is 24.83 mW (3.42 mW), and the dynamic range is 61 dB (55.5 dB). For pseudodifferential-output high-Q configuration, the measured quality factor Q can be as high as 360 with f₀=222.7 MHz. When Q=94, the power consumption is 56.2 mW and the measured dynamic range is 57.8 dB for 12.5 V supply voltage     

1.5-V high-performance SC filters in BiCMOS technology

The authors describe two low-voltage switched-capacitor (SC) filters: one can operate from a minimum supply of 1.5 V and the other from a minimum supply of 2 V (for typical parameter values). Both filters use a fully differential architecture and are fabricated in a standard BiCMOS technology. The lowest supply filter, operated from a 2-V supply, has an SNR (signal-to-noise ratio) of 92 dB and a THD (total harmonic distortion) of -70 dB for a 2.4-V_pp differential signal. Power consumption and area per pole are 60 μW and 0.18 mm², respectively, with a clock frequency of 447 kHz. The realized filters can be used as building blocks to implement more complex functions, like the active synthesis of a given impedance in line-fed telecom systems     

Compact low voltage four quadrant CMOS current multiplier

A new compact low voltage four quadrant current mode CMOS multiplier is presented. Post layout simulation in a CMOS 0.5 μm technology shows a linearity error lower than 0.9% for signal swings up to ±50 μA. The circuit operates at a supply of ±1.5 V, has a static power dissipation of 0.6 mW and a 1 dB bandwidth of 33 MHz     

An 81-MHz IF receiver in CMOS

An 81-MHz CMOS IF receiver for digital wireless applications is presented. The receiver consists of a continuous-time IF amplifier, a subsampling switched-capacitor gain stage, and a sixth-order bandpass ΣΔ A/D converter. Incorporating 24 dB of programmable gain, the receiver achieves 92 dB of dynamic range in a 200 kHz bandwidth. Due to its IF sampling nature, the reciever is immune to de offset, flicker noise, and errors due to mismatches between I and Q signal paths. By utilizing a pseudo two-path resonator architecture in the bandpass ΣΔ A/D converter, a stable passband center frequency which is immune to capacitor mismatch is achieved. Implemented in 0.8-μm CMOS, this chip uses a single 3 V supply and consumes 14.4 mW of power     

A 100-MHz bandpass sigma-delta modulator with a 75-dB dynamic range for IF receivers

A fourth-order switched-capacitor bandpassΣ△modulator is presented for digital intermediatefrequency (IF) receivers.The circuit operates at a sampling frequency of 100 MHz.The transfer function of the resonator considering nonidealities of the operational amplifier is proposed so as to optimize the performance of resonators.The modulator is implemented in a 0.13-μm standard CMOS process.The measurement shows that the signal-to-noise-and-distortion ratio and dynamic range achieve 68 dB and 75 dB,respectively,over a bandwidth of 200 kHz centered at 25 MHz,and the power dissipation is 8.2 mW at a 1.2 V supply.     

A compact low-power BiCMOS log-domain filter

A third-order Chebyshev filter based on the log-domain principle and integrated in a 1-μm BiCMOS process is presented. It has a nominal cutoff frequency of 320 kHz corresponding to a bias current of 1 μA, and can be frequency tuned over almost three decades up to about 10 MHz. It operates with a nominal supply voltage of 1.2 V, maintaining a dynamic range (DR) at 1% THD of 57 dB. For cutoff frequencies in the range of 10 kHz, the supply voltage can be reduced down to 0.9 V. The filter occupies an active area of 0.25 mm² and dissipates 23 μW, corresponding to a power consumption per pole and edge frequency of only 24 pJ. These results demonstrate the potential of log-domain filters for very low-voltage and low-power applications     

Real-time programmable low power SC bandpass filter

A real-time programmable switched capacitor (SC) second-order bandpass filter is presented. It is based on the voltage inverter switch (VIS) principle using inverse recharging devices. These devices are realized with dynamic amplifiers in order to achieve low power dissipation. The filter contains only grounded or virtually grounded network capacitances and, therefore, it is insensitive to the parasitic capacitances between the bottom plate of the implemented MOS capacitors and the substrate. The circuit offers digital programming capability (two Q factors and three center frequencies) and low power dissipation (185 /spl mu/W at a sampling frequency of 8 kHz and with a power supply voltage of 10 V). The filter has been integrated in CMOS metal-gate technology.     

A 1.5-V high drive capability CMOS op-amp

A novel CMOS operational amplifier with a 1.5 V power supply is presented. It is based on a folded-mirror transconductance amplifier and a high-efficiency output stage. The amplifier achieves an open-loop gain and a gain-bandwidth product higher than 65 dB and 1 MHz, respectively. In addition, a 1 V peak-to-peak output voltage into a 500 Ω and 50 pF output load is provided with a total harmonic distortion of -77 dB. This performance was achieved using maximum aspect ratios of 120/1.2 and 360/1.2 for the NMOS and PMOS transistors, respectively, and a quiescent current as low as 60 μA for the driver transistors. The amplifier was implemented in a standard 1.2 μm CMOS process with threshold voltages around 0.8 V. It dissipates less than 300 μW     

Passive CCD resonator filters

Novel passive recursive CCD bandpass filters have been realized using standard two-level-polysilicon gate NMOS technology. A Chebyshev bandpass (w/SUB rel,/ /SUB 3/ /SUB dB/=3.1 percent) and a fully integrated CCD signal filter with an extremely narrow 3 dB bandwidth of 97 Hz (Q=1350) at 131.85 kHz center frequency were implemented by means of cascaded CCD resonators. The latter chip contains the necessary clock generation and biasing circuitry realized with dynamic circuit techniques to achieve low power consumption (40 mW per filter). Performing all filtering operations exclusively in the charge domain ensures filter passivity. An extremely stable center frequency and a bandwidth independently controlled by a capacitance ratio are the special advantages of such filters.     

Low power CMOS preamplifier for neural recording applications

A fully-differential bandpass CMOS (complementary metal oxide semiconductor) preamplifier for extracellular neural recording is presented. The capacitive-coupled and capacitive-feedback topology is adopted. The preamplifier has a midband gain of 20.4 dB and a DC gain of 0. The -3 dB upper cut-off frequency of the preamplifier is 6.7 kHz. The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands. It has an input-referred noise of 8.2 μVrms integrated from 0.15 Hz to 6.7 kHz for recording the local field potentials and the mixed neural spikes with a power dissipation of 23.1 μW from a 3.3 V supply. A bandgap reference circuitry is also designed for providing the biasing voltage and current. The 0.22 mm2 prototype chip, including the preamplifier and its biasing circuitry, is fabricated in the 0.35-μm N-well CMOS 2P4M process.     

A low power tunable Gm–C filter based on double CMOS inverters in 0.35?μm

In this article, an inverter based transconductor using double CMOS pair is proposed for implementation of a second order lowpass G_m?CC Filter. The proposed operational transconductance amplifier (OTA) and biquad filter are designed using standard 0.35???m CMOS technology. Simulation results demonstrate the central frequency tunability from 10?kHz to 2.8?MHz which is suitable for the wireless specifications of Bluetooth (650?kHz), CDMA 2000 (700?kHz) and Wideband CDMA (2.2?MHz) applications. The power consumption of the filter is 445?nW and 178???W at 10?kHz and 2.8?MHz from 3.3?V supply voltage, respectively. The active area occupied by the designed filter on the silicon is 215?×?720???m². The proposed approach guarantees the upper bound on THD to be ?40?dB for 300?mVpp signal swing. Employing the double CMOS pair in the inverters causes PSRR to reach 68.6?dB which is higher than similar works.     

CMOS continuous-time current-mode filters for high-frequencyapplications

Design considerations for high-frequency CMOS continuous-time current-mode filters are presented. The basic building block is a differential current integrator with its gain constant set by a small-signal transconductance and a gate capacitance. A prototype fifth-order low-pass ladder filter implemented in a standard digital 2 μm n-well CMOS process achieved a -3 dB cutoff frequency (f ₀) of 42 MHz; f₀ was tunable from 24 to 42 MHZ by varying a reference bias current from 50 to 150 μA. Using a single 5 V power supply with a nominal reference current of 100 μA, the five-pole filter dissipated 25.5 mW. The active filter area was 0.056 mm²/pole. With the minimum input signal defined as the input-referred noise integrated over a 40 MHz bandwidth, and the maximum input signal defined at the 1% total intermodulation distortion (TIMD) level, the measured dynamic range was 69 dB. A third-order elliptic low-pass ladder filter was also integrated in the 2 μm n-well CMOS process to verify the implementation of finite transmission zeros     

Integrated CMOS SC filter with 170 kHz cutoff frequency

Based on the theory of switched capacitor (SC) filters using voltage invertor switches (VIS) a third order lowpass filter has been designed and integrated in a standard CMOS metal gate technology. The filter uses a bottom plate stray-insensitive VIS and requires only unity gain buffers. Performance parameters of an integrated version are: cutoff frequency 170 kHz, dynamic range 70 dB, and power dissipation 12 mW.