Au/Pt/AuGe/Ni中Pt扩散阻挡层对n-GaAs欧姆接触的影响

The multi-layer metals of Ni/Au Ge/Pt/Au with a Pt diffusion barrier layer of ohmic contact to n-GaAs were studied. The surface morphology and ohmic contact resistivity of multi-layer metals were characterized, with and without the Pt diffusion barrier layer for comparison. The SEM and EDS measurements show the Pt diffusion barrier layer can block the interdiffusion of atoms in multi-layer metals, and improve the surface morphology.The TLM results show that the samples with a Pt diffusion barrier layer have uniform ohmic contact resistance,indicating that the Pt diffusion barrier layer can increase the repetition and uniformity of ohmic contact to n-GaAs,and improve the thermal stability and reliability of GaAs-based devices.     

Ti/WSi/Ni ohmic contact to n-type SiCN

Ti/WSi/Ni contact to n-type SiCN was investigated using the circular transmission line method. Current–voltage characteristics, X-ray diffraction and X-ray photoelectron spectroscopy were used to characterize the contacts before and after annealing. It is shown that the conducting behavior of the contacts is dependent on the annealing temperature. After annealing at 900 ℃ or above, ohmic contacts with specific contact resistivity were achieved. The 1000-℃-annealed contact exhibits the lowest specific contact of 3.07E-5 Ω? cm2. The formation of ohmic contact with low specific contact resistivity was discussed.     

InP基转移电子器件接触性能的优化研究

The effect of the annealing time and annealing temperature on Ni/Ge/Au electrode contacts deposited on the n-type InP contact layer has been studied using a circular transmission line model. The minimum specific contact resistance of 3.210 7 cm2was achieved on the low-doped n-type InP contact layer with a 40 s anneal at 425 ℃. In order to improve the ohmic contact and reduce the difficulty in the fabrication of the high doped InP epi-layer, the doping concentration in the InP contact layer was chosen to be 51018cm 3in the fabrication of transferred electronic devices. Excellent differential negative resistance properties were obtained by an electron beam evaporating the Ni/Ge/Au/Ge/Ni/Au composite electrode on an InP epi-layer with a 60 s anneal at 380 ℃.     

Lateral diffusion effects in AuGe based source-drain contacts to AllnAs/InGaAs/InP doped channel MODFETs

We have investigated the formation of source-drain AuGe/Au and Ni/AuGe/Ni/Au alloyed ohmic contacts to AlInAs/InGaAs/InP doped channel MODFETs, and observed lateral diffusion of the contact system after the standard annealing procedure at the temperature range of 185 to 400°C. Auger depth profiling of contacts annealed at 250°C, revealed that Au(Ge) diffused through the top InGaAs and AlInAs layers into the active InGaAs layer, but had reduced penetration into the AlInAs buffer layer. This reduction in diffusion along the depth axis at the AlInAs buffer layer boundary is believed to result in enhanced lateral diffusion and the observed lateral encroachment of the contacts. Both Au and Ni containing contact systems showed similar behavior in terms of lateral diffusion with encroachment extending between 0.25 and 0.5 μm at the periphery of the contacts for annealing temperatures between 300 and 400°C. A controlled ramp-to-peak temperature annealing procedure is developed to suppress such lateral diffusion effects. Low temperature annealing (250°C) using this procedure resulted in equally low contact resistance values (∼0.1Θ-mm) and no lateral diffusion. It is concluded that in thin multilayered structures the modified annealing procedure presented here, is necessary for optimal ohmic contact formation.     

The behavior of Ni/Au contacts under rapid thermal annealing in GaN device structures

The effect of rapid thermal annealing (RTA) on Ni/Au contacts on P-type GaN was investigated in terms of surface morphology and diffusion depth of metallic species. Ni/Au contacts were evaporated on the P-type 0.5 μm thick top layer of a GaN P/N homojunction. Optical micrographs revealed that the contact morphology degrades when annealed above 800°C for 1 min. At the same time, both Ni and Au atoms strongly diffuse in the P-type layer and even can reach the junction for a 1 min long annealing at 900°C, therefore making the junction structure unoperable. This behavior was evidenced using the Auger voltage contrast (AVC) technique.     

Effect of annealing temperature on Ti/Al/Ni/Au ohmic contacts on undoped AlN films

The Ti/Al/Ni/Au metals were deposited on undoped AlN films by electron beam evaporation. The influence of annealing temperature on the properties of contacts was investigated. When the annealing temperatures were between 800 and 950℃, the AlN-Ti/Al/Ni/Au contacts became ohmic contacts and the resistance decreased with the increase of annealing temperature. A lowest specific contacts resistance of 0.379 Ω·cm² was obtained for the sample annealed at 950℃. In this work, we confirmed that the formation mechanism of ohmic contacts on AlN was due to the formation of Al-Au, Au-Ti and Al-Ni alloys, and reduction of the specific contacts resistance could originate from the formation of Au₂Ti and AlAu₂ alloys. This result provided a possibility for the preparation of AlN-based high-frequency, high-power devices and deep ultraviolet devices.     

Ohmic contact behaviour of Co/C/4H-SiC structures

The electrical contact properties of Co/4H-SiC structures are investigated.A carbon interfacial layer between a Co film and SiC is used to improve the Ohmic contact properties significantly.The C film is deposited prior to Co film deposition on SiC using DC sputtering.The high quality Ohmic contact and specific contact resistivity of 2.30×10^-6Ω·cm² are obtained for Co/C/SiC structures after two-step annealing at 500℃for 10 min and 1050℃for 3 min.The physical properties of the contacts are examined by using XRD.The results indicate that the Co-based metal contacts have better structural stability of silicide phases formed after the high temperature annealing and carbon-enriched layer is produced below the contact,playing a key role in forming an Ohmic contact through the reduction of effective Schottky barrier height for the transport of electrons.The thermal stability of Au/Co/C/SiC Ohmic contacts is investigated.The contacts remain Ohmic on doped n-type(2.8×10¹⁸ cm^-3) 4H-SiC after thermal aging treatment at 500℃for 20 h.     

Ni(Pt) 锗硅化合物/Si1-xGex 接触电阻的测试

The electrical properties of Ni0.95Pt0.05-germanosilicide/Si1_xGex contacts on heavily doped p-type strained Sil-xGex layers as a function of composition and doping concentration for a given composition have been investigated. A four-terminal Kelvin-resistor structure has been fabricated by using the conventional com- plementary metal-oxide-semiconductor （CMOS） process to measure contact resistance. The results showed that the contact resistance of the Ni0.95Pt0.05-germanosilicide/Sil-xGex contacts slightly reduced with increasing the Ge fraction. The higher the doping concentration, the lower the contact resistivity. The contact resistance of the samples with doping concentration of 4×10^19 cm^-3 is nearly one order of magnitude lower than that of the sam- ples with doping concentration of 5 × 10^17 cm^-3. In addition, the influence of dopant segregation on the contact resistance for the lower doped samples is larger than that for the higher doped samples.     

Effects of rapid thermal annealing on ohmic contact of AIGaN/GaN HEMTs

Ohmic contacts with Ti/Al/Ti/Au source and drain electrodes on A1GaN/GaN high electron mobility transistors （HEMTs） were fabricated and subjected to rapid thermal annealing （RTA） in flowing N2. The wafer was divided into 5 parts and three of them were annealed for 30 s at 700, 750, and 800 ℃, respectively, the others were annealed at 750 ℃ for 25 and 40 s. Due to the RTA, a change from Schottky contact to Ohmic contact has been obtained between the electrode layer and the A1GaN/GaN heterojunction layer. We have achieved a low specific contact resistance of 7.41 × 10-6Ω cm2 and contact resistance of 0.54 Ω.mm measured by transmission line mode （TLM）, and good surface morphology and edge acuity are also desirable by annealing at 750 ℃ for 30 s. The experiments also indicate that the performance of ohmic contact is first improved, then it reaches a peak, finally degrading with annealing temperature or annealing time rising.     

INTERDIFFUSION OF THE p-InP WITH Au-Zn,Ti/Au,Pd/Au,Ti/Pd/Au AT INTERFACE AND THEIR ELECTRICAL PROPERTIES

In this report,the interdiffusion between the p-InP with Au-Zn,Ti/Au,Pd/Au and Ti/Pd/Au atinterface have been investigated by Auger electron spectroscopy and electron spectroscopy for chemicalanalysis.The surface morphology for the heat treatment are observed with scanning electron microscopy.It is found that the indiffusion of Au is easier than that of Pd and Ti and the outdiffusion of In is easierthan that of P.The combination state of In and Au is formed during the heat treatment of p-InP/Au-Zn.The effects of the alloying temperature and time on the specific contacts resistance of p-InP/Au-Zn systemare studided.The low specific contact resistance,p_c=2.4-2.7×10~(-4)Ω-cm~2,is obtained when alloying at450℃ for 2 min or at 350℃ for 30 min.These results indicate that the specific contact resistance strongly depend on the“interdiffusiondegree”.The Zn in Au-Zn ahoy distributes onto the most surface layer of p-InP/Au-Zn system duringevaporation process and heat treatment.It may be one of the reasons for the higher specific contactsresistance.     

超薄SiO2/HfO2双层栅介质的时变击穿特性和击穿机制的研究

The characteristics of TDDB （time-dependent dielectric breakdown） and SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied. The EOT （equivalent-oxide-thickness） of the gate stack （Si/SiO2/HfOz/TiN/TiA1/TiN/W） is 0.91 am. The field acceleration factor extracted in TDDB experi- ments is 1.59 s.cm/MV, and the maximum voltage is 1.06 V when the devices operate at 125 ℃ for ten years. A detailed study on the defect generation mechanism induced by SILC is presented to deeply understand the break- down behavior. The trap energy levels can be calculated by the SILC peaks： one S1LC peak is most likely to be caused by the neutral oxygen vacancy in the HfO2 bulk layer at 0.51 eV below the Si conduction band minimum; another SILC peak is induced by the interface traps, which are aligned with the silicon conduction band edge. Fur- thermore, the great difference between the two SILC peaks demonstrates that the degeneration of the high-k layer dominates the breakdown behavior of the extremely thin gate dielectric.     

可重构双频段低噪声放大器的设计和实现

A reconfigurable dual-band LNA is presented. The LNA employs switching capacitors and circuit in to realize the dual-band operation. These methodologies are used to design and implement a reconfigurable LNA for IMT-A and UWB application. The LNA is implemented using TSMC-0.13 μm CMOS technology. Measured performance shows an input matching of better than -13.5 dB, a voltage gain of 18-22.8 dB, with an NF of 4.3-4.7 dB in the band of 3.4-3.6 GHz, and an input matching of better than -9.7 dB, a voltage gain of 14.7-22.4 dB, and with an NF of 3.7-4.9 dB in the band of 4.2-4.8 GHz. According to the measure results, the proposed LNA achieves dual-band operation, and it proves the feasibility of the proposed topology.     

一种电流复用共栅低噪声放大器的低功耗433/915-MHz射频前端的设计

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier(LNA),current-reuse V –I converter,active double balanced mixer and transimpedance amplifier for short range device(SRD) applications.With the proposed current-reuse LNA,the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices.The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm2.Operating in 433 MHz band,the measurement results show the RF front-end achieves a conversion gain of 29.7 dB,a double side band noise figure of 9.7 dB,an input referenced third intercept point of –24.9 dBm with only 1.44 mA power consumption from 1.8 V supply.Compared to other reported front-ends,it has an advantage in power consumption.     

Ranking Potential Reply-Providers in Community Question Answering System

Community Question Answering （CQA） websites have greatly facilitated users＇ lives, with an increasing number of people seeking help and exchanging ideas on the Internet. This newlymerged community features two characteristics： social relations and an ask-reply mechanism. As users＇ behaviours and social statuses play a more important role in CQA services than traditional answer retrieving websites, researchers＇ concerns have shifted from the need to passively find existing answers to actively seeking potential reply providers that may give answers in the near future. We analyse datasets derived from an online CQA system named ＂Quora＂, and observed that compared with traditional question answering services, users tend to contribute replies rather than questions for help in the CQA system. Inspired by the findings, we seek ways to evaluate the users＇ ability to offer prompt and reliable help, taking into account activity, authority and social reputation char- acteristics. We propose a hybrid method that is based on a Question-User network and social network using optimised PageRank algorithm. Experimental results show the efficiency of the proposed method for ranking potential answer-providers.     

一个全差分可编程的多通道神经信号记录芯片

A multi-channel,fully differential programmable chip for neural recording application is presented.The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain,eight 4thorder Bessel switch capacitor filters,an 8-to-1 analog time-division multiplexer,a fully differential successive approximation register analog-to-digital converter(SAR ADC),and a serial peripheral interface for communication.The neural recording amplifier presents a programmable gain from 53 dB to 68 dB,a tunable low cut-off frequency from 0.1 Hz to 300 Hz,and 3.77 μVrms input-referred noise over a 5 kHz bandwidth.The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4.The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process.We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.     

一种应用于GPS接收机的高线性度SiGe HBT低噪声放大器

A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of ＋7.8 dBm and an input third-order intercept point of ＋1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.     

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.     

一种不带校正SFDR为85.2dB的14位100兆流水线模数转换器

This paper describes a 14-bit 100-MS/s calibration-free pipelined analog-to-digital converter （ADC）. Choices for stage resolution as well as circuit topology are carefully considered to obtain high linearity without any calibration algorithm. An adjusted timing diagram with an additional clock phase is proposed to give residue voltage more settling time and minimize its distortion. The ADC employs an LVDS clock input buffer with low-jitter consideration to ensure good performance at high sampling rate. Implemented in a 0.18-μm CMOS technology, the ADC prototype achieves a spurious free dynamic range （SFDR） of 85.2 dB and signal-to-noise-and-distortion ratio （SNDR） of 63.4 dB with a 19.1-MHz input signal, while consuming 412-mW power at 2.0-V supply and occupying an area of 2.9 × 3.7 mm^2.