低温ECL电路的直流特性分析

本文在对低温双极晶体管的直流特性的分析基础上,推导出ECL电路在低温下的直流解析模型,并与实验结果和计算机模拟结果进行了比较,还对SPICEⅡ模型在低温下的修正和低温ECL电路的设计进行了一些探讨。     

A fully compensated active pull-down ECL circuit withself-adjusting driving capability

A new active pull-down emitter-coupled logic (ECL) circuit having full compensation against fluctuations in supply voltage and temperature is proposed. This circuit needs no capacitors but a feed-back circuit to adjust its pull-down capability to its load capacitance. The speed performance is compared between the active pull-down ECL circuit and the conventional ECL circuit using 0.8 μm SPICE parameters. The active pull-down ECL circuit is twice as fast as the conventional ECL circuit under the load capacitance of 0.8 pF with the same power dissipation. The relation between the power dissipation and the operating frequency is compared among the CMOS, the conventional ECL, and the active pull-down ECL circuits. The comparison adapts a new method in which the circuit parameters are optimized at each operating frequency. The SPICE simulation using this new method shows the conventional ECL circuit has a lower power dissipation than the CMOS circuit, even in the low operating frequency region of 100 MHz. The new active pull-down ECL circuit has the lowest power dissipation among the three circuits. The power dissipation of this circuit shows 47% lower than the CMOS circuit and 29% lower than the conventional ECL circuit at the operating frequency of 600 MHz and the load capacitance of 0.8 pF     

低温ECL电路的特性分析及优化设计

本文在对双极器件各参数的低温特性的详细分析基础上，对低温ＥＣＬ电路的直流和瞬态特性进行了理论和实验的研究，并据此对电路进行了统一的优化设计。     

High-speed low-power charge-buffered active-pull-down ECI circuit

A high-speed, low-power, charge-buffered active-pull-down ECL (emitter-coupled logic) circuit is described. The circuit features a charge-buffered coupling between the common-emitter node of the switching transistors and the base of an active-pull-down n-p-n transistor. This coupling scheme provides a much larger dynamic current than what can be reasonably achieved through the capacitor coupling and a DC path to alleviate the AC-testing requirement. Furthermore, the dynamic current is utilized effectively by the logic stage, thus allowing a reduction in the power consumption of the logic stage without sacrificing the switching speed. Based on a 0.8-μm double-poly self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 37% improvement in both the speed and load driving capability for a loaded gate compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed     

On the profile design and optimization of epitaxial Si- andSiGe-base bipolar technology for 77 K applications. II. Circuitperformance issues

For pt.I see ibid., vol.40, no.3, p.525-41 (1993). The circuit performance issues associated with optimizing epitaxial Si- and SiGe-base bipolar technology for the liquid-nitrogen temperature environment are examined in detail. It is conclusively demonstrated that the notion that silicon-based bipolar circuits perform poorly at low temperatures is untrue. Transistor frequency response is examined both theoretically and experimentally, with particular attention given to the differences between SiGe and Si devices as a function of temperature. ECL and NTL ring oscillator circuits were fabricated for each of the four profiles described in pt.I. The minimum ECL gate delay for a SiGe base is essentially unchanged from its room-temperature value. ASTAP models were used to explore circuit operation under typical wire loading. The results indicate that epitaxial-base bipolar technology offers significant leverage for future cryogenic applications     

Analyzing ECL's noise margin

Although CMOS technologies continue to dominate VLSI, advanced bipolar technologies are emerging as a viable alternative, thanks to improvements in circuit density and yield. These bipolar technologies are chiefly directed towards very high-speed applications, mostly in the form of emitter coupled logic (ECL) or current mode logic (CML) circuit configurations. A key advantage of the ECL/CML circuit configuration is its ability to operate reliably at low voltage swings. There is, however, a trade-off: as the voltage swing is reduced, so also is the ability of the circuit to withstand unwanted input voltage variations, i.e., noise. While the speed and power dissipation characteristics of ECL/CML have received considerable analytical and quantitative treatment in the literature, the noise margin has earned little analytical attention. In this article, the authors derive an improved expression for the static noise margin of ECL     

具有有源下拉电路和图腾柱式输出结构的CML门电路

本文提出了一种高速低功耗、具有有源下拉电路和图腾柱式输出结构的ＣＭＬ（简称ＭＣＭＬ）门电路；详细地阐述了ＭＣＭＬ门电路的工作原理和优点；列出了电路仿真结果；并对其电路特性与ＥＣＬ和ＡＰＤ－ＥＣＬ电路进行了比较。     

Advanced bipolar circuits

Advances in high-speed, low-power bipolar circuits aimed at achieving superior power-delay performance and load-driving capability over conventional ECL and NTL circuits are reviewed. The basic principles underlying power/speed improvement including charge-buffering, DC/AC-coupled active pull-down schemes, and complementary push-pull approaches, are examined. The utilization and combination of these basic principles to form various high-speed, low-power circuits in both n-p-n-only and complementary circuit configurations and the design tradeoffs of these circuits are discussed     

高性能硅双极器件的发展

以ECL电路为主,讨论了硅双极器件近期的发展。简述了VLSI中ECL电路结构和性能之后,着重讨论双极器件的按比例缩小、结构的改进以及相关的工艺技术的发展,最后分析了双极器件的低温工作性能。     

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters

The design and performance of a high-speed 1 M*1-bit SRAM with ECL I/O are described. The 6.5*16.5-mm/sup 2/ chip was fabricated with a 0.8- mu m BiCMOS process technology. A modified double-word-line (MDWL) structure and a bit-line peripheral circuitry with normally-on bit-line equalization circuit are used to achieve high-speed read operation. The read speed is further enhanced by a novel ECL-to-CMOS-level converter with a double-latch configuration. The converter dissipates no DC current and contributes to low power consumption together with an automatic power-saving function, utilizing the address transition detection (ATD) technique. The access time is typically 8 ns, and the active power is 500 mW at 50 MHz.<>     

Theory of differential current switches and logic design of ternary ECL circuits at switch level

Starting from the viewpoint that the switch states and signal values in a digital circuit should be described separately by two different kinds of variable, the interaction between the switching element and signal in multi-valued ECL circuits is analysed and two types of connection operations, threshold switching operation and current switching operation, are proposed. The properties and circuit realizations of these new operations are discussed and the theory of differential current switches applicable to ECL circuits is established. Examples of basic ternary ECL circuits confirm that this theory can effectively guide the logic design of ternary ECL circuits at switch level. The circuits are verified by using the SPICE II program. They have the same logic level difference and transient characteristic as binary ECL circuits. Since the multi-valued ECL circuit uses only one set of power supply and can set several threshold values by using reference levels, it can be fabricated using conventional ECL techniques and is compatible with binary ECL circuits.     

250 MHz CCD driver

A DC to 250 MHz CCD driver, designed for 10 V output into 50 pF capacitive loading, is described. The circuit features ECL compatible input, less than 2 W quiescent power dissipation, and a total component cost under sixty dollars per driver.     

On the low-temperature static and dynamic properties ofhigh-performance silicon bipolar transistors

In a study performed over the temperature range of 400 to 77 K, Si bipolar transistors were found to have near-ideal characteristics at low temperatures with β as high as 80 at 77 K. Detailed calculations indicate that the conventional theory of the temperature dependence of β does not match the data. The discrepancy can be removed if it is assumed that a phenomenological thermal barrier to hole injection is present. Emitter-coupled logic (ECL) ring oscillators are functional at 85 K with no degradation in speed until about 165 K when compared to 358 K (85°C). Calculations using a delay figure of merit indicate that f_T, R_b, and C_c are the delay components most affected by low-temperature operation. The feasibility of reduced logic swing operation of bipolar circuits at low temperatures is examined. It is found that successful ECL circuit operation at reduced logic swings is possible provided emitter resistance is kept small and can be used to enhance low-temperature power-delay performance. These data suggest that conventionally designed high-performance bipolar devices are suitable for the low-temperature environment     

一种用于AC/DC控制器中电压基准源的设计

提出了一种新颖的可用于AC/DC控制芯片中的基准电压源电路。此电路以PTAT（proportional to absolutetemperature）电流为偏置电流,利用二极管连接的MOS晶体管迁移率和阈值电压的温度系数可相互补偿的特性,产生与温度无关的栅源电压。该电路结构简单,既无启动电路也无运放,避免了运放失调对基准源的影响,设计采用CSMC0.5μm BCD工艺。仿真结果表明,该基准电压源具有较低的温度系数和高电源电压抑制比,可作为AC/DC控制芯片中迟滞比较器的参考源。     

一种用于非致冷红外焦平面读出电路的带隙基准源

设计了一种用于新型非致冷红外焦平面阵列读出电路的低温漂低压带隙基准电路.提出了同时产生带隙基准电压源和基准电流源的技术.通过改进带隙基准电路中的带隙负载结构及基准核心电路,可以分别对基准电压和基准电流进行温度补偿.在0.5μm CMOS N阱工艺条件下,采用Spectre软件进行了模拟验证.仿真结果表明,在3.3 V条...     

基于温度补偿的无运放低压带隙基准源设计

设计了一种带温度补偿的无运放低压带隙基准电路。提出了同时产生带隙基准电压源和基准电流源的技术,通过改进带隙基准电路中的带隙负载结构以及基准核心电路,基准电压和基准电流可以分别进行温度补偿。在0.5μmCMOS N阱工艺条件下,采用spectre进行模拟验证。仿真结果表明,在3.3V条件下,在-20～100℃范围内,带隙基准电压源和基准电流源的温度系数分别为35.6ppm/℃和37.8ppm/℃,直流时的电源抑制比为-68dB,基准源电路的供电电压范围为2.2～4.5V。     

一种超高速÷2ECL分频器

本文描述了采用氧化物隔离等平面S工艺、离子注入技术和快速热退火,以及采用电阻网络反馈信号的改进型D触发器的优化电路的设计方法研制的1500MHz÷2ECL分频器。电路在常温下的工作速度超过2000MHz,即使在85℃的高温条件下,其最高工作频率也超过1900MHz,完全满足了用户的要求。     

1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-μm CMOS

This paper describes the design and the implementation of input-output (I/O) interface circuits for serial data links in the gigabit-per-second range. The cells were implemented in a 3.3-V 0.35-μm CMOS technology in a couple of test chips. The transmitter is fully compatible (DC coupling) with 100K positive emitter-coupled logic (PECL) systems and it is based on the voltage-switching principle in order to allow different termination schemes besides the canonical ECL termination, i.e., 50-Ω toward (V_DD-2) V. The addition of some circuit techniques such as dynamic biasing and strobed current switching boosts the dynamic performance of the basic voltage-switching scheme and relaxes the requirements for a high bias current and large-size output devices at the same time. Moreover, thanks to the developed reference circuit, using both feedforward and feedback controls, the output levels are within the 100K tolerance over the full range of process, supply voltage, and temperature (PVT) variations without resorting to external components or on-chip trimming. The receiver cell is based on a complementary-differential architecture providing high speed and low error on the duty cycle of the CMOS output signal. The integrated receiver-transmitter chain exhibits a maximum toggle frequency of 1 GHz, while a chip-to-chip transmission link using the developed I/O interface was tested up to 1.2 Gb/s     

Capacitor-free level-sensitive active pull-down ECL circuit withself-adjusting driving capability

This paper introduces a new self-adjusting active pull-down scheme for ECL circuit. The circuit offers self-terminating dynamic pull-down action by sensing the output level rather than using traditional load-dependent capacitive coupling. No capacitor or large resistor is required, and therefore it adds no process complexity and no area penalty. Implemented in an ECL gate array in a 1.2 μm double-poly self aligned bipolar technology, the circuit offers 300-ps delay at a power consumption of 1 mW/gate under FO=1 and C_L=0.55 pF loading condition. This is a 4.4 times speed improvement over the conventional ECL circuit. Furthermore, the circuit consumes only 0.25 mW for a gate speed of 700 ps/gate, which is a 1/7.8 power reduction compared with the conventional ECL circuit. The circuit requires a regulated reference voltage, which is also studied