THE QUATERNARY INTERFACE TECHNIQUE IN ECL INTEGRATED CIRCUITS

The theory of differential current switches which applies to the design of multivaluedECL circuits is introduced.In this theory,the switching state of differential transistor pairand signal in ECL circuits are described by switching variables and quaternary signal variables,respectively.he connection operations between the two kinds of variables are introduced todescribe the action process between switching element and signal in the circuits.Based on thistheory,two kinds of interface circuits-2-4 encoder and 4-2 decoder are designed.The computersimulation for the designed circuits by using SPICE program confirms that both circuits havecorrect logic functions,desired DO transfer characteristics and transient characteristics.Theseinterface circuits are compatible with binary circuits in the integrated process,the power supplyequipment,the logic stage and the transient characteristic.Therefore,they can be used as input-output interface of the existing binary ECL integrated circuits so as to decrease the number ofpins of a chip and the connections between chips.     

ECL集成电路的四值接口技术

本文介绍了适用于多值ECL电路设计的差动电流开关理论。在该理论中,分别用开关变量和四值信号变量来描写ECL电路中差动晶体管对的开关状态和信号,并引入此两类变量之间的联结运算,以描写电路内部开关元件与信号的相互作用过程。基于该理论,本文对两种接口电路2-4编码器和4-2译码器进行了设计。应用SPICE程序对设计电路的计算机模拟表明,两种电路均具有正确的逻辑功能、理想的DC转移特性和瞬态特性。由于该接口电路具有与二值电路兼容的集成工艺、电源设备、逻辑级差和瞬态特性,因此它可用作现有二值ECL集成电路的输入输出接口,从而达到减少芯片的引脚数和片间连接的目的。     

基于开关信号理论的三值电流型CMOS电路设计

本文应用开关信号理论对电流型CMOS电路中MOS传输开关管与电流信号之间的相互作用进行了分析,并提出了适用于电流型CMOS电路的传输电流开关理论。应用该理论设计的三值全加器等电路具有简单的电路结构和正确的逻辑功能,从而证明了该理论在指导电流型CMOS电路在开关级逻辑设计中的有效性。     

基于比较器的四值电流型CMOS加减电路设计

该文通过对电流型CMOS电路的阈值控制引入了多值电流型比较器。与2值逻辑电路相比,多值逻辑电路的单条导线允许更多的信息传输。相较于电压信号,电流信号易实现加、减等算术运算,在多值逻辑的设计上更加方便。同时提出了基于比较器的4值基本单元设计方法,实现了4值取大、取小以及反向器的设计,在此基础上设计实现了加法器和减法器。该设计方法在2值、3值以及n值逻辑上同样适用。实验结果表明所设计的电路具有正确的逻辑功能,较之相关文献电流型CMOS全加器有更低的功耗和更少的晶体管数。     

基于开关信号理论的四值ECL电路

从一个有效的多值代数系统应能反映多值电路中的物理过程的这一原则出发,本文提出了一组可以描写多值ECL电路中信号与开关元件间相互作用的运算。讨论了这些运算的物理对应及有关性质,并由此建立了适用于ECL电路的开关信号理论。本文设计了若干基本四值ECL电路,用SPICE程序模拟证明了它们均具有正确的逻辑功能与理想的DC特性。     

DESIGN OF TERNARY CURRENT-MODE CMOS CIRCUITS BASED ON SWITCH-SIGNAL THEORY

By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is suitable to current-mode CMOS circuits is proposed. Thecircuits, such as ternary full-adder etc., designed by using this theory have simpler circuit struc-tures and correct logic functions. It is confirmed that this theory is efficient in guiding the logicdesign of current-mode CMOS circuits at switch level.     

高信息密度的ECL集成电路设计

本文从多值逻辑能提高集成电路处理信息量的观点出发对三值ECL高速集成电路进行研究.文中提出符合双极型晶体管工作原理的基本运算,并讨论了有关性质.在此基础上提出差动电流开关理论,并用于设计若干基本三值ECL电路.使用SPICE 2G5程序的计算机模拟表明,这些电路具有正确的逻辑功能及理想的静态与瞬态特性.     

对称传输电流开关理论与对称三值电流型CMOS算术电路

本文应用开关－信号理论建立了基于对称三值逻辑适用于对称三值电流型ＣＭＯＳ电路开关级设计的对称传输电流开关理论。     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

Transistor-tunnel-diode ternary-logic circuits

Two new basic circuits for ternary-logical operations are described. Analogue simulation and experimental measurements confirm that the switching speeds of the ternary circuits can be comparable with those in similar binary circuits. It is concluded that a marginal improvement in processing rate may be achieved with ternary logic using transistor-tunnel-diode logic circuits.     

基于传输开关理论的电流型多值CMOS电路设计

本文以开关信号理论为指导，对电流型CMOS电路中开关变量和信号变量的相互作用进行了分析，并引入了适用于CMOS电路的电流开关理论。基于电流传输开关理论，对几类重要的三值CMOS电路进行了设计，结果表明，应用该理论能获得简单的电路设计。从而进一步完善了开关级逻辑电路设计的研究。     

基于开关信号理论的电流型CMOS多值施密特电路设计

以开关信号理论为指导,建立了描述电流型CMOS多值施密特电路中阈值控制电路的电流传输开关运算.在此基础上,提出了新的电流型CMOS三值和四值施密特触发器设计.所设计的电路可提供多值电流和电压输出信号,回差电流的大小只需通过改变MOS管的尺寸比来调节.所提出的电路较之以往设计具有结构简单,回差值调整容易以及可在较低电压下工作等特点.采用TSMC 0.25 μ m CMOS工艺参数和1.5V电压的HSPICE模拟结果验证了所提出设计方案的有效性和电路所具有的理想回差特性.     

三值绝热多米诺文字运算电路开关级设计

通过对绝热多米诺电路和多值电路的研究,提出一种新颖的低功耗三值文字运算电路的开关级设计方案。该方案首先通过开关—信号理论推导出逻辑0和2的文字运算电路开关级结构式及电路;然后利用三种文字运算之间互斥与互补的约束关系得到逻辑1的文字运算输出信号,同时通过波形转换电路使电路的输出转换为较规则的缓变梯形波;最后利用Spice软件对所设计的电路进行仿真,结果显示所设计的三值绝热多米诺文字运算电路具有正确的逻辑功能,与常规多米诺三值文字运算电路相比,能耗节省约39%。     

THE RESEARCH ON TERNARY TTL SCHMITT CIRCUITS

By analyzing the threshold-jumping of Schmitt circuits, this paper indicates that the core element realizing this function in binary TTL Schmitt circuits is the differential current switch with controllable threshold. Based on the characteristic having two kinds of signal-detection threshold in ternary TTL circuits, a ternary TTL Schmitt circuit having twice reactions of threshold-jumping is designed. The simulation with PSPICE proves that the designed circuit has ideal function of Schmitt circuits.     

多值逻辑基本运算的神经网络实现

多层感知器神经网络是典型的人工神经网络模型。算后，将其推广到多值逻辑。根据感知器神经元的分类特点，系统中的基本运算，从而也实现了任意三值逻辑函数。本文在分析二值感知器神经网络实现二值数字逻辑运采用三层前向稳健感知器神经网络实现了三值格代数。     

基于开关信号理论的控阈技术与三值ECL施密特电路

基于开关信号理论，本文对ＥＣＬ电路中的阈值控制进行了研究，建立了用于描述旋密特电路中阈值可控开关工作过程听数学表示式。在此基础上设计了具有二次跳阈反应的三值ＥＣＬ旋密特电路。对所设计电路的ＰＳＰＩＣＥ模拟表明它具有理想的施密特电路特性。     

Design of ternary CMOS circuits based on transmission function theory

This paper presents threshold comparison operation, transmission operation and union operation which can be used to describe the function of MOS transistors in a pass-transistor network. The relative properties and circuit realizations of these operations, and the transmission function expression by use of these operations are discussed. A transmission function theory suitable to CMOS network synthesis is proposed. This paper also discusses the simplification of ternary functions and proposes minimized design of some basic ternary CMOS circuits. The computer simulation using SPICE2G5 has confirmed that these circuits have desirable DC transfer characteristics.     

A 4-bit/spl times/4-bit multiplier and 3-bit counter in Josephson threshold logic

A fast Josephson circuit using a threshold logic is developed for application to a multiplier and a binary counter. The former is a typical combinational circuit and the latter is a typical sequential circuit. The junction and barrier materials used were Nb-AlO/SUB X/-Nb. An optimized asymmetric two-junction interferometer maximized the operating margin of the threshold gate. A speed-up junction was introduced to decrease the switching delay without sacrificing the operating margin. A dumping resistor, which was inserted parallel to the input signal line of the threshold gate between its two terminals, decreased the reflection of the input signal caused by the gate inductance, thereby ensuring the margin and speed. To demonstrate the high-speed possibility of the Josephson threshold logic, a high-speed experiment for the circuits was performed. The multiplier demonstrated 210-ps operation.     

采用vMOS管的多值计数器设计

通过对νMOS管特性和多值逻辑电路设计原理的研究,本文提出一种新型多值计数器的设计方案。该方案利用νMOS管具有多输入栅加权信号控制及浮栅上的电容耦合效应等特性,结合二值逻辑编码方法,实现电路的多值输出。用PSPICE对所设计的电路模拟验证,结果表明,所设计的电路逻辑功能正确,结构简单,功耗低,且通用性强,易于实现。     

基于模代数的三值维持阻塞触发器及其应用

本文给出了基于模代数理论的三值维持阻塞触发器,并将其应用到时序逻辑电路设计中。由于多值模代数中的两个基本运算和运算结果均为多值信号,所以它的应用避免了以往在采用基于Ｐｏｓｔ代数的三值触发器时,由于输入、输出信号不匹配而必须增加附加编码电路的问题。设计实例表明,该触发器具有更强的逻辑功能,它使得移位寄存器类的时序电路设计得以显著简化。