A 130-mm2, 256-Mbit NAND flash with shallow trenchisolation technology

A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 μm is achieved with 0.25-μm STI. The memory cell is shrunk to 0.29 μm², which realizes a 130-mm² , 256-Mbit flash memory. Peripheral transistors are scaled with memory cells in order to reduce fabrication process steps. A voltage down converter, which generates 2.5-V constant internal power source, is applied to protect the scaled transistors. An improved bit-line clamp sensing scheme achieves 3.8-μs first access time in spite of long and tight pitch bit-line. A 1-kbyte page mode with 35-ns serial data out realizes 25-Mbyte/s read throughput. An incremental step pulse with a bit by bit verify scheme programs 1-k cells in 1-V Vt distribution within 200 μs. That realizes 4.4-Mbyte/s programming throughput     

Driving source-line cell architecture for sub-1-V high-speedlow-power applications

A novel SRAM cell architecture for sub-1-V high-speed operation is proposed that uses neither low-V_th MOSFETs nor modified cell layout patterns. A source-line, connected to the source terminals of the driver MOSFETs is controlled so that it is negative and floating in the read and write cycles, respectively. This improved the bit-line access time by 1/4-1/2 at supply voltages of 0.5-1.0 V. Limiting the bit-line swing reduces by 1/10 the writing power needed to charge them and allows faster write-recovery, as well. The achievability of low-power 100-MHz operation over a wide range of supply voltages is demonstrated     

A 4-ns 4K×1-bit two-port BiCMOS SRAM

The authors introduce a two-port BiCMOS static random-access memory (SRAM) cell that combines ECL-level word-line voltage swings and emitter-follower bit-line coupling with a static CMOS latch for data storage. With this cell, referred to as a CMOS storage emitter access cell, it is possible to achieve access times comparable to those of high-speed bipolar SRAMs while preserving the high density and low power of CMOS memory arrays. The memory can be read and written simultaneously and is therefore well-suited to applications such as high-speed caches and video memories. A read access time of 3.8 ns at a power dissipation of 520 mW has been achieved in an experimental 4K×1-bit two-port memory integrated in a 1.5-μm 5-GHz BiCMOS technology. The access time in this prototype design is nearly temperature-insensitive, increasing to only 4 ns at a case temperature of 100°C     

Cell-plate-line/bit-line complementary sensing (CBCS) architecturefor ultra low-power DRAMs

In the realization of gigabit scale DRAMs, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecture called cell-plate-line/bit-line complementary sensing (CBCS) architecture which realizes drastic array power reduction for both read/write operations and refresh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%, This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core design realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced     

采用源极增强带带隧穿热电子注入编程的新型p沟选择分裂位线NOR快闪存贮器

提出一种新型的PMOS选择分裂位线NOR结构快闪存贮器,具有高编程速度、低编程电压、低功耗、高访问速度和高可靠性等优点.该结构采用源极增强带带隧穿热电子注入进行编程,当子位线宽度为128位时,位线漏电只有3.5μA左右,每位编程功耗为16.5μW,注入系数为4×10-4,编程速度可达20μs,存贮管的读电流可达60μA/μm以上.分裂位线结构和低编程电压使得该结构具有很好的抗位线串扰特性和可靠性.     

采用源极增强带带隧穿热电子注入编程的新型p沟选择分裂位线NOR快闪存贮器

提出一种新型的PMOS选择分裂位线NOR结构快闪存贮器,具有高编程速度、低编程电压、低功耗、高访问速度和高可靠性等优点.该结构采用源极增强带带隧穿热电子注入进行编程,当子位线宽度为128位时,位线漏电只有3.5μA左右,每位编程功耗为16.5μW,注入系数为4×10-4,编程速度可达20μs,存贮管的读电流可达60μA/μm以上.分裂位线结构和低编程电压使得该结构具有很好的抗位线串扰特性和可靠性.     

An eight-bit prefetch circuit for high-bandwidth DRAM's

A low-power and area-efficient data path circuit for high-bandwidth DRAMs is described. For fast burst read operations, eight data per data I/O are stored in local latches placed close to sense amplifiers. As implemented in a 16-Mb synchronous DRAM (SDRAM), this 8-b prefetch circuit allows an early precharge command and a fast access time because it provides low-capacitance data lines for segmented bit-line pairs. At a column address strobe (CAS) latency of two and a burst length of four, the SDRAM demonstrates 100-MHz seamless read operations from different row addresses, because the row precharge and read access latencies are hidden during the burst cycles. The layout of the prefetch circuit is not limited by the bit-line pitch, and data path circuits are connected by a second-metal layer over the memory cells. As a result, a small chip size of 99.98 mm² is attained. Low-capacitance data lines and small local latches result in low active power. In a 100-MHz full-page burst mode, the SDRAM with a 1 M×16-b configuration dissipates 60 mA at 3.6 V     

A 23-ns 256 K EPROM with double-layer metal and address transition detection

A 23-ns 256 K CMOS EPROM has been developed on a 0.8- mu m double-layer metal technology. The product employs a differential configuration and an interleaved FAMOS cell with a high read current of 80 mu A at V/sub g/=4 V, V/sub d/=1.5 V, 25 degrees C. The array is organized as 32 K*8. Fast access time is obtained by a combination of advanced technology, double-layer metal (DLM), differential sensing, address transition detection (ATD), and a ground-switched decoding scheme. DLM is used to strap word lines. High performance is obtained by reducing bit-line length to 256 cells, with 2048 cells per word line. The combination of strapped word lines along with short bit lines produces very fast access time. The active power is 75 mA, and standby power is 9 mA at room temperature. The die size is 116*339 mil/sup 2/ (25.4 mm/sup 2/).<>     

A high-speed sensing scheme for 1T dynamic RAMs utilizing theclamped bit-line sense amplifier

A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to the initial bit-line difference voltage. The CBLSA maintains a low impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power     

A four-phase handshaking asynchronous static RAM design forself-timed systems

The motivation of designing asynchronous memory arises from the recent development of asynchronous processors. As different from the conventional design, the proposed asynchronous static RAM can: (1) communicate with other asynchronous systems based on a four-phase handshaking control protocol; and (2) generate the read/write completion signals with increased average speed by the variable bit-line load concept. The techniques investigated include (1) dual-rail voltage sensing completion detection for read operation and (2) multiple delays completion generation for write operation. In this paper, the performances of these techniques are evaluated for 1 Mb memory with four regions of bit-line segmentation. The simulated and measured results are presented and compared     

A 14-ns 14-Mb CMOS DRAM with 300-mW active power

A 4-Mb high-speed DRAM (HSDRAM) has been developed and fabricated by using 0.7-μm L_eff CMOS technology with PMOS arrays inside n-type wells and p-type substrate plate trench cells. The 13.18-mm×6.38-mm chip, organized as either 512 K word×8 b or 1 M word×4 b, achieves a nominal random-access time of 14 ns and a nominal column-access time of 7 ns, with a 3.6-V V_cc and provision of address multiplexing. The high level of performance is achieved by using a short-signal-path architecture with center bonding pads and a pulsed sensing scheme with a limited bit-line swing. A fast word-line boosting scheme and a two-stage word-line delay monitor provide fast word-line transition and detection. A new data output circuit, which interfaces a 3.6-V V_cc to a 5-V bus with an NMOS-only driver, also contributes to the fast access speed by means of a preconditioning scheme and boosting scheme. Limiting the bit-line voltage swing for bit-line sensing results in a low power dissipation of 300 mW for a 60-ns cycle time     

A 1-V, 100-MHz, 10-mW cache using a separated bit-line memoryhierarchy architecture and domino tag comparators

A 1-V 16-KB (L2) 2-KB (L1) four-way set-associative cache was fabricated using a 0.25-μm CMOS technology for future low-power high-speed microprocessors. Effective latency of 6.9 ns and power consumption of 10 mW at 100 MHz are obtained at a supply voltage of 1 V. This performance is achieved by using a new separated bit-line memory hierarchy architecture (SBMHA) that speeds up latency and reduces power consumption, and domino tag comparators (DTC's) that reduce the power dissipation of tag comparisons     

X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs

In an SRAM circuit, the leakage currents on the bit lines are getting increasingly prominent with the dwindling of transistors' threshold voltages as the technology scales down to 90 nm and beyond. Excessive bit-line leakage current results in slower read operations or even functional failure. In this paper, we present a new technique, called X-calibration, to combat this phenomenon. Unlike the previous method that attempts to compensate the leakage current directly, this scheme first transforms the bit-line leakage current into an equilibrium offset voltage across the bit-line pair, and then simple circuitry is utilized to cancel this offset accurately at the input of the sense amplifier so that the sensing is not affected by the bit-line leakage. SPICE simulation of a 1 Kbit SRAM macro shows that this X-calibration scheme can handle 83% higher bit-line leakage current than the previous bit-line leakage compensation scheme. Measurement results of the test chip show that the SRAM macro adopting X-calibration scheme can cope with up to 320 $mu{hbox{A}}$ bit-line leakage current.      

A dual Vt disturb-free subthreshold SRAM with write-assist and read isolation

This paper presents a new dual Vt 8T SRAM cell having single bit-line read and write,in addition to Write Assist and Read Isolation (WARI).Also a faster write back scheme is proposed for the half selected cells.A high Vt device is used for interrupting the supply to one of the inverters for weakening the feedback loop for assisted write.The proposed cell provides an improved read static noise margin (RSNM) due to the bit-line isolation during the read.Static noise margins for data read (RSNM),write (WSNM),read delay,write delay,data retention voltage (DRV),leakage and average powers have been calculated.The proposed cell was found to operate properly at a supply voltage as small as 0.41 V.A new write back scheme has been suggested for half-selected cells,which uses a single NMOS access device and provides reduced delay,pulse timing hardware requirements and power consumption.The proposed new WARI 8T cell shows better performance in terms of easier write,improved read noise margin,reduced leakage power,and less delay as compared to the existing schemes that have been available so far.It was also observed that with proper adjustment of the cell ratio the supply voltage can further be reduced to 0.2 V.     

A 12-ns ECL I/O 256 K×1-bit SRAM using a 1-μm BiCMOStechnology

An ECL (emitter-coupled-logic) I/O 256K×1-bit SRAM (static random-access memory) has been developed using a 1-μm BiCMOS technology. The double-level-poly, double-level-metal process produces 0.8-μm CMOS effective gate lengths and polysilicon emitter bipolar transistors. A zero-DC-power ECL-to-CMOS translation scheme has been implemented to interface the ECL periphery circuits to the CMOS decode and NMOS matrix. Low-impedance bit-line loads were used to minimize read access time. Minimization of bit-line recovery time after a write cycle is achieved through the use of a bipolar/CMOS write recovery method. Full-die simulations were performed using HSPICE on a CRAY-1     

A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converterin a 0.25-μm digital CMOS process

The design of a high-speed analog-to-digital (A/D) converter for hard disk drive read channels is described. The A/D converter uses a flash architecture with an interleaved sample and hold and interpolating comparator pre-amplifiers. It has 6 bits of resolution at full speed as well as a 7 bit mode operating at a lower speed. The 7 bit mode is useful for servo signal processing. This A/D converter has been implemented in a four-level metal single-poly 0.25 μm CMOS technology. The device operates at a speed of up to 700 MSamples/s in the 6 bit mode while maintaining a signal-to-noise-plus-distortion rate (SNDR) of greater than 35 dB at input frequencies of up to one-fourth the sampling rate. In the 7 bit mode, the device operates at up to 200 MSamples/s with a SNDR greater than 41 dB. It occupies an active area of 0.45 mm² and consumes less than 187 mW of power     

一种高速只读存储器拓扑结构的设计

随着只读存储器密度越来越大,对读取速度的要求越来越高,位线大电容逐渐成为影响只读存储器读取速度的关键问题.设计了一种存储器拓扑结构,这种结构通过改变存储单元读取点的位置,能有效避免位线大电容充放电对读取速度的不利影响,极大地缩短了读取周期,提高了只读存储器的读取速度.该拓扑结构的优势在TSMC 0.13μm工艺仿真库里得到验证.     

A Low-Power SRAM Using Bit-Line Charge-Recycling

Low-power SRAM design is crucial since it takes a large fraction of total power and die area in high-performance processors. Reducing voltage swing of the bit-line is an effective way to save the power dissipation in write cycles. Voltage swing reduction of bit-lines is, however, limited due to possible write-failures. We propose a new low-power SRAM using bit-line charge recycling (CR-SRAM) for the write operation. In the proposed write scheme, differential voltage swing of a bit-line is obtained by recycled charge from its adjacent bit-line capacitance, instead of the power line. Applying such a charge recycling technique to the bit-line significantly reduces write power. A test chip with 32 Kbits (256 rows x 128 columns) is fabricated and measured in 0.13 mum CMOS to demonstrate operation of the proposed SRAM. Measurement results show 88% reduction in total power during write cycles compared to the conventional SRAM (CON-SRAM) at V_DD = 1.5 V and f = 100 MHz.     

An 18 ns 4K/spl times/4 CMOS SRAM

A high-speed 11-mm/SUP 2/ 4K/spl times/4 CMOS static RAM fabricated developed. This circuit uses improved circuit techniques to with a single-polysilicon, single-metal process has been obtain a typical 18-ns access time with only 250 mW of active power. Among the topics discussed are the smallest single-polysilicon static RAM cell reported to date; the use of address transition assistance for equalization and boosting; a short-delay, positive-feedback boosted word line; high-speed predecoded row and column decoders; new fully compensated bit-line loads and column presence amps; and an easily implemented redundancy scheme using laser fusing techniques.     

A 16-ns 1-Mb CMOS EPROM

A 16-ns 1-Mb CMOS EPROM has been developed utilizing high-speed circuit technology and a double-metal process. In order to achieve the fast access time, a differential sensing scheme with address transition detection (ATD) is used. A double-word-line structure is used to reduce word-line delay. High noise immunity is obtained by a bit-line bias circuit and data-latch circuit. Sufficient threshold voltage shift (indispensable for fast access time) is guaranteed by a threshold monitoring program (TMP) scheme. The array is organized as 64 K×16 b, which is suitable for 32-b high-performance microprocessors. The active power is 425 mW, the programming time is 100 μs, and the chip size is 4.94×15.64 mm²