Low-frequency noise in TFSOI lateral n-p-n bipolar transistors

Low-frequency (1/f) noise is characterized as a function of base current density (J_B) on thin-film-silicon-on-insulator (TFSOI) lateral bipolar transistors. In the low injection region of operation, the noise power spectral density was proportional to J_B ^1.8 for J_B<0.4 μA/μm², which suggest that the noise in these devices is primarily dominated by a uniform distribution of noise sources across the emitter-base area. However in the high current region of operation (J_B>0.4 μm²), the noise bias dependence shifts to J_B ^1.2, indicating current crowding effects, alter the contribution of noise sources near the extrinsic base link region of the device. In addition to the expected 1/f noise and shot noise, we have observed a bias dependent generation-recombination (Gm) noise source in some of the devices. This G/R noise is correlated to random-telegraph-signal (RTS) noise resulting from single trapping centers, located at or near the spacer oxide and/or the Si to SIMOX interface, which modulate the emitter-base space charge region     

A new SPICE MOSFET Level 3-like model of HEMT's for circuitsimulation

A fully analytical model for the current-voltage (I-V) characteristics of HEMT's is presented. It uses a polynomial expression to model the dependence of sheet carrier concentration (n_s) in the two-dimensional electron gas (2-DEG) on gate voltage (V_G ). The resultant I-V relationship incorporates a correction factor α analogous to SPICE MOSFET Level 3 model and is therefore more accurate than models assuming a linear n_s-V_G dependence leading to square law type I-V characteristics. The model shows excellent agreement with experimental data over a wide range of bias. Further, unlike other models using nonlinear n_s-V_G dependence, it neither uses fitting parameters nor does it resort to iterative methods at any stage. It also includes the effects of the extrinsic source and drain resistances. Due to its simplicity and similarity in formulation to the SPICE MOSFET Level 3 model, it is ideally suited for circuit simulation purposes     

0.10 μm graded InGaAs channel InP HEMT with 305 GHzfT and 340 GHz fmax

We report here 305 GHz f_T, 340 GHz f_max, and 1550 mS/mm extrinsic g_m from a 0.10 μm In_xGa _1-xAs/In_0.62Al_0.48As/InP HEMT with x graded from 0.60 to 0.80. This device has the highest f_T yet reported for a 0.10 μm gate length and the highest combination of f _T and f_max reported for any three-terminal device. This performance is achieved by using a graded-channel design which simultaneously increases the effective indium composition of the channel while optimizing channel thickness     

A channel resistance derivative method for effective channel lengthextraction in LDD MOSFETs

A channel resistance derivative method for extracting the electrical effective channel length and series resistance is proposed, and demonstrated on an advanced 0.35 μm LDD CMOS technology. A clear graphic image of the L_EFF and R_SD is obtained directly from the measured channel resistance and its derivative with respect to the gate bias. The method also provides guidelines for the proper gate bias range selection in traditional L_EFF extraction techniques     

Device parameter extraction in the linear region of MOSFET's

A self-consistent technique is proposed to extract device parameters from the I-V characteristics of MOSFET's in the linear region. The three parameters V_T, B_m(=β₀ ) and R_m are extracted from the implicitly weighed least square curve fitting of r_D against 1/(V_G-V _T-αV_D). The series resistance R, the factor &thetas; of the V_G dependent β, and L_eff are then obtained by comparing the long and short channel devices, Reasonable values are obtained for five technologies, and general agreement with Taur's method is confirmed. Based on the finding, a quick parameter extraction method using only three {r_D, V_G } data sets is proposed     

Epitaxially-grown GaN junction field effect transistors

Junction field effect transistors (JFETs) are fabricated on a GaN epitaxial structure grown by metal organic chemical vapor deposition (MOCVD). The dc and microwave characteristics of the device are presented. A junction breakdown voltage of 56 V is obtained corresponding to the theoretical limit of the breakdown field in GaN for the doping levels used. A maximum extrinsic transconductance (g_m ) of 48 mS/mm and a maximum source-drain current of 270 mA/mm are achieved on a 0.8 μm gate JFET device at V_GS=1 V and V_DS=15 V. The intrinsic transconductance, calculated from the measured g_m and the source series resistance, is 81 mS/mm. The f_T and f_max for these devices are 6 GHz and 12 GHz, respectively. These JFET's exhibit a significant current reduction after a high drain bias is applied, which is attributed to a partially depleted channel caused by trapped hot-electrons in the semi-insulating GaN buffer layer. A theoretical model describing the current collapse is presented, and an estimate for the length of the trapped electron region is given     

A new polycrystalline silicon TFT with a single grain boundary inthe channel

A new excimer laser annealing method, which results in large lateral polysilicon grains exceeding 1.5 μm, has been proposed and polycrystalline silicon thin film transistors (poly-Si TFTs) with a single grain boundary in the channel have been successfully fabricated. The proposed method employs a lateral grain growth phenomenon obtained by excimer laser irradiation on an amorphous silicon layer with pre-patterned aluminum film. The aluminum patterns act as a masking layer of the incident laser beam for the selective melting of the amorphous silicon layer. Uniform and large grains are obtained near the edge of the aluminum patterns. When two aluminum patterns are separated by a 2 μm space, the solidified region (i.e., poly-Si channel) exhibits a single grain boundary. The n-channel poly-Si TPT fabricated by the proposed method shows considerably improved I-V characteristics, such as high field effect mobility exceeding 240 cm²/Vs     

Transconductance enhancement due to back bias for submicron NMOSFET

For the first time, a new phenomenon of transconductance enhancement due to back bias found in submicron MOSFET's is reported. A two-dimensional numerical simulation has been performed to investigate the origin of this observation. The enhancement of the channel potential gradient is verified to be the main reason responsible for this anomalous transconductance enhancement effect. Moderate channel doping concentrations (5×10¹⁶~5×10¹⁷ cm^-3), short channel lengths (submicron regime), and operation under small drain bias are three key conditions for the maximum transconductance enhancement due to the back bias to occur. A conventional linear I-V model, which employs an effective channel length defined by the source/drain metallurgical junctions and bias-independent source/drain extrinsic resistance is not able to predict such characteristics     

Singlemode channel waveguides and electrooptic modulators in KTiOPO4 for the short visible wavelength region

Single-mode channel waveguides at short visible wavelengths have been fabricated in KTiOPO₄ by Rb&rlhar2;K ion exchange in mixed melts of RbNO₃-KNO₃-Ba(NO₃)₂ . The technological parameters have been chosen by means of theoretical WKB- and “effective index” calculations concerning the singlemode region of the effective channel waveguide index N₀₀ at the given wavelength. Great diffusion anisotropy and small dispersion of the surface refractive index change guarantee singlemode operation of the very same channel waveguide from the blue up to the red. Typical attenuation of about 2.0 dB/cm for TM- and 1.5 dB/cm for TE polarization was obtained at λ=0.5145 μm. Light-induced refractive index changes (photorefractive effect) have been determined as a function of time, wavelength, guided optical mode intensity and temperature. The light-induced effects in Rb&rlhar2;K ion-exchanged channel waveguides in KTiOPO₄ are about two orders of magnitude smaller than those in annealed proton-exchanged channel waveguides in LiNbO₃. Electrooptic phase modulators have been successfully investigated concerning dynamic V_π measurements, the electric-optical field overlap and dc-drift phenomena. Design, fabrication and experimental results of integrated-optic Mach-Zehnder-interferometer modulators for short visible wavelengths are presented     

A novel self-aligned bottom gate poly-Si TFT with in-situ LDD

A lithography independent self-aligned bottom gate thin film transistor (SABG-TFT) technology is proposed and experimentally demonstrated. The unique feature of the technology is the formation of self-aligned and symmetrical lightly doped source/drain (LDD) structure without any additional photolithographic or implantation steps. Thus, the number of masks used in the technology is the same as that in a conventional top gate TFT technology. Moreover, devices formed by the proposed method have thick source/drain and a thin channel region for providing low source/drain resistance and improved I-V characteristics. P-channel TFT devices are fabricated using a simple low temperature (⩽600°C) process. The fabricated SABG-TFT exhibits symmetrical transfer characteristics when the polarity of source/drain bias is reversed. The effective mobility and on-off current ratio of the devices are about 35 cm²/V-s and 6×10⁶ respectively     

Fully self-aligned tri-layer a-Si:H thin-film transistors withdeposited doped contact layer

We demonstrate a new self-aligned TFT process for hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs). Two backside exposure photolithography steps are used to fabricate fully self-aligned tri-layer TFTs with deposited n⁺ contacts. Since no critical data alignment is required, this simple process is well suited to fabrication of short channel TFTs. We have fabricated fully self-aligned tri-layer a-Si:H TFTs with excellent device performance, and contact overlaps <1 μm. For a 20-μm channel length TFT with an a-Si:H thickness of 13 nm, the linear region (V_DS=0.1 V) and saturation region (V_DS=25 V) extrinsic mobility values are both 1.2 cm²/V-s, the off currents are <1 pA, and the on/off current ratio is >10⁷     

Performance and off-state current mechanisms of low-temperatureprocessed polysilicon thin-film transistors with liquid phase depositedSiO2 gate insulator

Polysilicon thin-film transistors (poly-Si TFT's) with liquid phase deposition (LPD) silicon dioxide (SiO₂) gate insulator were realized by low-temperature processes (<620°C). The physical, chemical, and electrical properties of the new dielectric layer were clarified. The low-temperature processed (LTP) poly-Si TFT's with W/L=200 μm/10 μm had an on-off current ratio of 4.95×10 ⁶ at V_D=5 V, a field effect mobility of 25.5 cm ²/V·s at V_D=0.1 V, a threshold voltage of 6.9 V, and a subthreshold swing of 1.28 V/decade at V_D=0.1 V. Effective passivation of defects by plasma hydrogenation can improve the characteristics of the devices. The off-state current (I_L) mechanisms of the LTP poly-Si TFT's were systematically compared and clarified. The I_L is divided into three regions; the I_L is attributable to a resistive current in region I (low gate bias), to pure thermal generation current in region II (low drain bias), and to Frenkel-Poole emission current in region III (high gate bias and drain bias)     

Submicrometer poly-Si CMOS fabrication with low-temperature laserdoping

The laser doping process for submicrometer CMOS devices with leakage currents as low as 10^-12 A/μm for both n-channel and p-channel devices is discussed. The I-V characteristics are comparable to those of poly-Si devices fabricated using ion implantation and high-temperature annealing processes. The laser-induced melting of predeposited impurity doping (LIMPID) process was used to fabricate submicrometer polycrystalline-Si CMOS devices. This process uses a very low temperature, so no dopant atom can diffuse along the grain boundaries in the solid region. The use of stacked Al/SiO₂ films as a protection layer made it possible to reduce the leakage current from several tens of picoamperes per micrometer to 1 pA/μm     

A new Z11 impedance technique to extract mobility andsheet carrier concentration in HFETs and MESFETs

Conventional techniques to extract channel mobility, μ, and sheet carrier concentration, n_s, in heterostructure field-effect transistors (HFETs) do not account for the distributed nature of the device. This can result in substantial errors. To address this, we have developed a new technique that consists of measuring the gate-to-source impedance with the drain floating (Z₁₁) over a broad frequency range. A transmission line model (TL model) is fitted to Re[Z₁₁], thus obtaining the gate capacitance and channel resistance (and consequently μ(V_GS) and n_s(V _GS)) in a single measurement. We demonstrate this technique in InAlAs-InGaAs on InP HFET's. The TL model faithfully represents Z₁₁ from 100 Hz to 15 MHz. Our technique can easily be automated and thus is a good tool for accurate charge control in an industrial environment     

A new technique for measuring MOSFET inversion layer mobility

An experimental technique for accurately determining both the inversion charge and the channel mobility μ of a MOSFET is presented. With this new technique, the inversion charge is measured as a function of the gate and drain voltages. This improvement allows the channel mobility to be extracted independent of drain voltage V_DS over a wide range of voltages (V_DS=20-100 mV). The resulting μ(V_GS) curves for different V_DS show no drastic mobility roll-off at V _GS near V_TH. This suggests that the roll-off seen in the mobility data extracted using the split C- V method is probably due to inaccurate inversion charge measurements instead of Coulombic scattering     

Degradation of InGaAs/InP double heterojunction bipolar transistorsunder electron irradiation

The dc characteristics of InGaAs/InP double heterojunction bipolar transistors (DHBTs) are studied under high-energy (~1 MeV) electron irradiation up to a fluence of 14.8×10¹⁵ electrons/cm ². The devices show an increase in common-emitter current gain (h_fe) at low levels of dose (<10¹⁵ electrons/cm²) and a gradual decrease in h_fe and an increase in output conductance for higher doses. The decrease in h _fe is as much as ~80% at low base currents (~10 μA) after a cumulative dose of 14.8×10¹⁵ electrons/cm². The observed degradation effects in collector current-voltage (I-V) characteristics are studied quantitatively using a simple SPICE-like device model. The overall decrease in h_fe is attributed to increased recombination in the emitter-base junction region caused by radiation-induced defects. The defects introduced in the collector-base junction region are believed to be responsible for the observed increase in the output conductance     

Partially depleted SOI NMOSFET's with self-aligned polysilicon gateformed on the recessed channel region

A new SOI NMOSFET with a “LOCOS-like” shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, we developed a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3 μm SOI devices with V_z of 0.773 V and T_ox=7.6 nm is 360 μA/μm at V_GS=3.5 V and V _DS=2.5 V. Improved breakdown characteristics were obtained and the BV_DSS (the drain voltage for 1 nA/μm of I_D at T_GS=0 V) of the device with L_eff=0.3 μm under the floating body condition was as high as 3.7 V     

A novel structure of silicon field emission cathode with sputteredTiW for gate electrode and TEOS oxide for gate dielectric

A novel silicon field emission cathode structure with a narrow spacing between tip and gate electrode is proposed, based on the filling characteristics of the sputtered Ti_0.1W_0.9 beneath the disc-shaped tip-mask oxide. Without advanced lithography technologies, the hole diameter of the gate is reduced to a sub-half-micrometer of ~0.4 μm from an initial tip-mask size of ~1.2 μm, and the gate electrode easily approaches the cathode, leading to a low-voltage operation. A uniform and stable field emission cathode is obtained using well-established VLSI process technologies. The current-voltage (I-V) characteristics of the cathodes show low turn-on voltages of ~30 V     

High-performance, 0.1 μm InAlAs/InGaAs high electron mobilitytransistors on GaAs

This letter describes the material characterization and device test of InAlAs/InGaAs high electron mobility transistors (HEMTs) grown on GaAs substrates with indium compositions and performance comparable to InP-based devices. This technology demonstrates the potential for lowered production cost of very high performance devices. The transistors were fabricated from material with room temperature channel electron mobilities and carrier concentrations of μ=10000 cm² /Vs, n=3.2×10¹² cm^-2 (In=53%) and μ=11800 cm²/Vs, n=2.8×10¹² cm^-2 (In=60%). A series of In=53%, 0.1×100 μm² and 0.1×50 μm² devices demonstrated extrinsic transconductance values greater than 1 S/mm with the best device reaching 1.074 S/mm. High-frequency testing of 0.1×50 μm² discrete HEMT's up to 40 GHz and fitting of a small signal equivalent circuit yielded an intrinsic transconductance (g_m,i) of 1.67 S/mm, with unity current gain frequency (f_T) of 150 GHz and a maximum frequency of oscillation (f_max) of 330 GHz. Transistors with In=60% exhibited an extrinsic g_m of 1.7 S/mm, which is the highest reported value for a GaAs based device     

Measurements and modeling of the n-channel MOSFET inversion layermobility and device characteristics in the temperature range 60-300 K

Discussed is the use of the high-frequency split C-V method to measure accurately the effective mobility of the n-channel MOS transistor as a function of temperature, bulk charge Q _b, and inversion layer charge Q_i. The experimental data for Q_b and Q_i were verified by comparison with the results of numerical simulation. The results of the measurements were used to develop the mobility model, which is accurate in the 60-300 K temperature range. The proposed mobility model incorporates Coulombic, lattice, and surface roughness scattering modes and generalizes the previous model, which was limited to low-temperature operation of the MOSFET. The deviation from the universal (for different back biases) μ(E_eff) dependence, which becomes more pronounced at low temperatures and low E_eff, is included in the model and can be associated with the Coulomb scattering mechanism. The proposed model is verified by comparison of experimental data and simulated MOSFET I-V characteristics for different temperatures