Partially depleted SOI NMOSFET's with self-aligned polysilicon gateformed on the recessed channel region

A new SOI NMOSFET with a “LOCOS-like” shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, we developed a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3 μm SOI devices with V_z of 0.773 V and T_ox=7.6 nm is 360 μA/μm at V_GS=3.5 V and V _DS=2.5 V. Improved breakdown characteristics were obtained and the BV_DSS (the drain voltage for 1 nA/μm of I_D at T_GS=0 V) of the device with L_eff=0.3 μm under the floating body condition was as high as 3.7 V