双极型压控晶体管直流特性的数值模拟

本文采用数值计算和解析分析相结合的方法,建立了新型功率半导体器件－－有型压控晶体管（ＢＪＭＯＳＦＥＴ）电流－电压特性的数值分析模型;运用Ｍａｔｈｅｍａｔｉｃｓ数学分析软件,模拟得出ＢＪＭＯＳＦＥＴ电压转移特性曲线和电压输出特性曲线;得出的结果说明在相同的器件结构尺寸和工作情况下,与功率ＭＯＳ晶体管相比,导通电压略有增加,但电流容量增加较大。     

BJMOSFET温度特性分析及计算机模拟

对兼有双极型和场效应型两种器件特点的双极MOS场效应晶体管(BJMOSFET)的电流和阈值电压的温度特性进行了详细分析．推导出它们随温度变化率的解析表达式。建立BJMOSFET的直流小信号模拟分析等效电路和频率特性模拟分析等效电路,采用通用电路仿真软件PSpice9,对BJMOSFET的输出特性、瞬态特性和幅频特性随温度的变化进行了计算机模拟,得到了随温度变化的特性曲线,并且理论分析与计算机模拟取得了一致的结果。相对传统MOSFET,证明了BJMOSFET具有较好的温度特性。     

Temperature Characteristics of BJMOSFET

The resolution expression for the temperature dependence of the current and threshold voltage is deduced as well as the analysis of temperature characteristics of BJMOSFET. Equivalent circuit of analysis and simulation has been established for the BJMOSFET temperature characteristics. By using the general circuit simulation software of PSpice9 and computer simulation, characteristic graphs of the BJMOSFET output characteristic, transient characteristic and amplitude-frequency characteristic with temperature variation are obtained. The results accorded very good with theoretical analysis and proved that BJMOSFET has better temperature characteristics than traditional MOSFET.     

基于SOI的双极场效应晶体管

在分析了双极型晶体管和场效应晶体管各自的特点和不足后，介绍了一种既具有双极型晶体管较大电流容量和功率输出，又具有场效应晶体管高输入阻抗的电子器件——双极MOS场效应晶体管(BJMOSFET)，同时指出体硅BJMOSFET的阳极扩散区与衬底之间存在较大的漏电流，可产生较大的寄生效应。提出了一种新型固体电子器件——基于SOI的BJMOSFET，分析了其工作原理j与体硅BJMOSFET比较，由于SOI技术完整的介质隔离避免了体硅器件中存在的大部分寄生效应，使基于SOI的BJMOSFET在体效应、热载流子效应、寄生电容、短沟道效应和闩锁效应等方面具有更优良的特性。     

RESEARCH OF BJMOSFET FREQUENCY CHARACTERISTICS

The parasitic capacitance effect and its influence to the performance have been investigated in Bipolar Junction Metal-Oxide-Semiconductor Field-Effect Transistor （BJMOSFET）. The frequency characteristic equivalent circuit and high frequency response model of BJMOSFET have been presented. The frequency characteristic of BJMOSFET is simulated using the multi-transient analytical method and PSPICE9 simulator. The conclusions that BJMOSFET owns less total capacitance, wider frequency band, better transient characteristic and better frequency responses are reached by comparing with the traditional MOSFET at the same structure parameters and bias conditions. BJMOSFET, as a novel promising high frequency device, would be desired to find application in future integrated circuit.     

A three-terminal intelligent power MOSFET with built-in reversebattery protection for automotive applications

An intelligent power MOSFET with built-in reverse battery protection, which is important for automotive power switches, has been developed. The protection is accomplished by integrating an additional power MOSFET in series with a power MOSFET and the control circuit of the additional power MOSFET. The reverse battery protection is achieved without using external control signals. The positive drain breakdown voltage for the proposed MOSFET is 71 V and the negative drain current at a drain voltage of -16 V is only -750 μA. The on-state resistance is 170 mΩ. This new intelligent power MOSFET can replace the conventional three-terminal power MOSFET's used in automotive applications     

IGBT SPICE model

During the last few years, great progress in the development of new power semiconductor devices has been made. The new generation of power semiconductors is capable of conducting more current and blocking higher voltage. The IGBT (insulated gate bipolar transistor) is an outgrowth of power MOSFET technology. More like a MOSFET than a bipolar transistor in structure, the IGBT has some of the electrical characteristics of both. Like a MOSFET, the gate of the IGBT is isolated, and drive power is very low. The on-state conduction voltage of an IGBT is similar to that of a bipolar transistor. However, SPICE users are constantly faced with the inability to analyze circuits that contain devices that are not in the SPICE library of the semiconductor models. With the authors' own computer program, a complete macromodel of the IGBT for the SPICE simulator has been computed. In this paper, a complete IGBT SPICE macromodel is described and verified with experimental results     

A reverse-voltage protection circuit for MOSFET power switches

When MOSFET is used as a power switch, it is essential to prevent reverse current flow through the parasitic body diodes under reverse voltage condition. A new built-in reverse voltage protection circuit for MOSFETs has been developed. In this design, an area-efficient circuit is used to automatically select the proper well bias voltage to prevent reverse current under the reverse-voltage condition. This built-in reverse protection circuit has been successfully implemented in a high-side power switch application using a 0.6-μm CMOS process. The die area of the protection circuit is only 2.63% of that of a MOSFET. The latch-up immunity is greater than +12 V and -10 V in voltage triggering mode, and greater than ±500 mA in current triggering mode. The protection circuit is not in series with the MOSFET switch, so that the full output swing and high power efficiency are achieved     

Threshold voltage model for deep-submicrometer fully depleted SOIMOSFET's

The threshold voltage, V_th, of fully depleted silicon-on-insulator (FDSOI) MOSFET with effective channel lengths down to the deep-submicrometer range has been investigated. We use a simple quasi-two-dimensional model to describe the V_th roll-off and drain voltage dependence. The shift in threshold voltage is similar to that in the bulk. However, threshold voltage roll-off in FDSOI is less than that in the bulk for the same effective channel length, as predicted by a shorter characteristic length l in FDSOI. Furthermore, ΔV_th is independent of back-gate bias in FDSOI MOSFET. The proposed model retains accuracy because it does not assume a priori charge partitioning or constant surface potential. Also it is simple in functional form and hence computationally efficient. Using our model, V _th design space for Deep-Submicrometer FDSOI MOSFET is obtained. Excellent correlation between the predicted V_th design space and previously reported two-dimensional numerical simulations using MINIMOS5 is obtained     

Thin-film quasi-SOI power MOSFET fabricated by reversed siliconwafer direct bonding

A quasi-SOI power MOSFET has been fabricated by reversed silicon wafer direct bonding. In this power MOSFET, the buried oxide under the channel and source regions is removed and the channel region is directly connected to the source body contact electrode to reduce the base resistance of the parasitic npn bipolar transistor. The quasi-SOI power MOSFET can suppress the parasitic bipolar action and shows lower specific on-resistance than that of the conventional SOI power MOSFET. The fabricated chip level quasi-SOI power MOSFET shows the specific on-resistance of 86 mΩ·mm² and on-state breakdown voltage of 30 V     

An analysis of the concave MOSFET

The electrical characteristics of the concave MOSFET are analyzed by the two-dimensional numerical method and the theoretical result is in reasonable agreement with the experimental result. Even if the channel length of the concave MOSFET is short, the obtained current-voltage characteristics of the concave MOSFET are quite similar to those of the long-channel normal MOSFET and can be approximated by the normal MOSFET formula. In short-channel concave MOSFET's, the threshold voltage lowering due to the short-channel effect is not observed. It is observed that the threshold voltage of the concave MOSFET depends strongly on the substrate bias voltage as compared with the long-channel normal MOSFET. These observed results are followed by the two-dimensional numerical analysis. The increase of the punch-through breakdown voltage as well as that of the surface induced avalanche breakdown voltage of the concave MOSFET is predicted theoretically. The equivalent circuit model of the concave MOSFET is shown and discussed.     

国产中高压抗辐照功率MOSFET单粒子效应

功率金属-氧化物半导体场效应晶体管(MOSFET)空间使用时易遭受重离子轰击产生单粒子效应(单粒子烧毁和单粒子栅穿)。本文对国产新型中、高压(额定电压250 V,500 V)抗辐照功率MOSFET的单粒子辐射效应进行了研究,并采取了有针对性的加固措施,使器件的抗单粒子能力显著提升。结果表明：对250 V KW2型功率MOSFET器件进行Bi粒子辐照,在栅压等于0 V时,安全工作的漏极电压达到250 V;对500 V KW5型功率MOSFET器件进行Xe粒子辐照,在栅压等于0 V时,安全工作的漏极电压达到400 V,并且当栅压为-15 V时,安全工作的漏极电压也达到400 V,说明国产中、高压功率MOSFET器件有较好的抗单粒子能力。     

Single-event burnout hardening of planar power MOSFET with partially widened trench source

We present a single-event burnout (SEB) hardened planar power MOSFET with partially widened trench sources by three-dimensional (3D) numerical simulation.The advantage of the proposed structure is that the work of the parasitic bipolar transistor inherited in the power MOSFET is suppressed effectively due to the elimination of the most sensitive region (P-well region below the N+ source).The simulation result shows that the proposed structure can enhance the SEB survivability significantly.The critical value of linear energy transfer (LET),which indicates the maximum deposited energy on the device without SEB behavior,increases from 0.06 to 0.7 pC/μm.The SEB threshold voltage increases to 120 V,which is 80％ of the rated breakdown voltage.Meanwhile,the main parameter characteristics of the proposed structure remain similar with those of the conventional planar structure.Therefore,this structure offers a potential optimization path to planar power MOSFET with high SEB survivability for space and atmospheric applications.     

A quasi-SOI power MOSFET for radio frequency applications formed byreversed silicon wafer direct bonding

A quasi-SOI power MOSFET for radio frequency (RF) applications was fabricated by reversed silicon wafer direct bonding (RSDB). Its breakdown voltage was more than twice that of the conventional SOI power MOSFET and its other dc characteristics were almost the same. Its maximum oscillation frequency was about 15% higher than that of the conventional SOI power MOSFET. The power-added efficiency (PAE) of the quasi- SOI power MOSFET was higher than the SOI one. It showed excellent PAE of 68% at a drain bias of 3.6 V     

适用于亚微米沟道MO SFET的阈值电压解析模型

本文利用本征函数方法,采取一定的边界条件,得到了二维泊松方程的解析解.并由此导得适用于亚微米沟道MOS场效应管阈值电压的解析表达式.本解析模型未引进复杂的几何结构参数及经验参数,适用于不同的衬底反偏电压、漏极电压等条件.这些结果与数值模拟的结果以及有关实验的结果符合得较好,对短沟道MOSFET的设计及性能的了解有实际参考价值.     

VHF高压双栅功率MOSFET的研制

采用硅栅结构的自对准离子注入工艺,研制成功了源漏击穿电压ＢＶＤＳ为１２０Ｖ、输出功率５．１Ｗ、功率增益８ｄＢ、跨导６５０ｍＳ、截止频率ｆＴ为２７０ＭＨｚ的高压双栅功率ＭＯＳＦＥＴ器件。介绍了器件结构参数和工艺参数的设计,给出了计算机数值分析结果。     

An analytic and accurate model for the threshold voltage of short channel MOSFETs in VLSI

Based on the two-dimensional Poisson equation, the surface potential distribution along the surface channel of a MOSFET has been analytically derived by assuming negligible source and drain junction depths and its minimum potential is then used to determine the threshold voltage. The existence of a minimum surface potential point along the channel of a MOSFET under an applied drain bias is consistent with the numerical results of the two-dimensional analysis. The effects of finite source and drain junction depths have been elegantly included by modifying the depletion capacitance under the gate and the resulted threshold voltage model has been compared to the results of the two-dimensional numerical analysis. It has been shown that excellent agreement between these results has been obtained for wide ranges of substrate doping, gate oxide thickness, channel length (< 1 μm), substrate bias, and drain voltage. Moreover, comparisons between the developed model and the existing experimental data have been made and good agreement has been obtained. The major advantages of the developed model are that no iterations and no adjustable fitting parameters are required. Therefore, this simple and accurate threshold voltage model will become a useful design tool for ultra short channel MOSFETs in future VLSI implementation.     

碳化硅MOSFET反型沟道迁移率的研究

SiC MOSFET是制作高速、低功耗开关功率器件的理想材料，然而，制作反型沟道迁移率较高的SiC MOSFET工艺尚未取得满意结果。通过在N0中高温退火可以显著地提高4H—SiC MOSFET的有效沟道迁移率；采用H2中退火制作的4H—SiC MOSFET阈值电压为3．1V，反型沟道迁移率高于100cm^2／Vs的栅压的安全工作区较宽。N20退火技术由于其的安全性而发展迅速并将取代N0。     

1200V大容量SiC MOSFET器件研制

采用平面栅MOSFET器件结构,结合优化终端场限环设计、栅极bus-bar设计、JFET注入设计以及栅氧工艺技术,基于自主碳化硅工艺加工平台,研制了1200V大容量SiC MOSFET器件.测试结果表明,器件栅极击穿电压大于55V,并且实现了较低的栅氧界面态密度.室温下,器件阈值电压为2.7V,单芯片电流输出能力达到50A,器件最大击穿电压达到1600V.在175℃下,器件阈值电压漂移量小于0.8V;栅极偏置20V下,泄漏电流小于45nA.研制器件显示出优良的电学特性,具备高温大电流SiC芯片领域的应用潜力.     

Low-voltage-swing monolithic dc-dc conversion

A low-voltage-swing MOSFET gate drive technique is proposed in this paper for enhancing the efficiency characteristics of high-frequency-switching dc-dc converters. The parasitic power dissipation of a dc-dc converter is reduced by lowering the voltage swing of the power transistor gate drivers. A comprehensive circuit model of the parasitic impedances of a monolithic buck converter is presented. Closed-form expressions for the total power dissipation of a low-swing buck converter are proposed. The effect of reducing the MOSFET gate voltage swings is explored with the proposed circuit model. A range of design parameters is evaluated, permitting the development of a design space for full integration of active and passive devices of a low-swing buck converter on the same die, for a target CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is lower than a standard full voltage swing. An efficiency of 88% at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 to 0.9 V with a low-swing dc-dc converter based on a 0.18-/spl mu/m CMOS technology. The power dissipation of a low-swing dc-dc converter is reduced by 27.9% as compared to a standard full-swing dc-dc converter.