一种适用于门级网表的混合式静态功耗优化方法

进入深亚微米集成电路设计阶段,静态功耗所占整体功耗的比例快速增大,使之成为当前设计流程中的关键优化步骤。该文提出一种适用于门级网表的混合式静态功耗优化方法。该方法结合了整数规划和启发式算法,以减小电路时序裕量的方式换取电路静态功耗的改善。整体优化流程从一个满足时序约束的设计开始,首先利用整数规划为网表中的逻辑门单元寻找一个较低静态功耗的最优替换单元;其次结合当前所用门单元和最优替换单元的物理和电学参数,按优先级方式逐层替换电路中所有的逻辑门节点;最后利用启发式方法修复可能出现的最大延时违规情况。整体优化流程将在上述步骤中不断迭代直至无法将现有时序裕量转换为功耗的改善。针对通用测试电路的实验结果表明,采用该方法优化后电路静态功耗平均减小10%以上,最高达26%;与其它方法相比,该方法不仅大幅降低了功耗,而且避免了优化后电路最大延时的过度恶化,其最大延时违反量小于5 ps。     

一种基于时延配置表的FPGA静态时序分析算法

为减小现场可编程门阵列(FPGA)关键路径的延时误差,提出一种基于时延配置表的静态时序分析算法。算法建立了一种基于单元延时与互连线延时配置表的时延模型。该模型考虑了工艺角变化对延时参数的影响,同时在时序分析过程中,通过分析路径始节点与终节点的时钟关系,实现了复杂多时钟域下的路径搜索与延时计算。实验结果表明,与公认的基于查找表的项目评估技术(PERT)算法和VTR算法相比,关键路径延时的相对误差平均减少了8.58%和6.32%,而运行时间平均仅增加了19.96%和9.59%。     

考虑工艺波动影响的RLC互连统计延时

该文提出了一种考虑工艺波动的统计RLC互连延时分析方法。文中首先给出了考虑工艺波动的寄生参数和矩的构建方法,然后基于Weibull分布给出了RLC互连的统计延时模型。所提方法同样适用于已有的延时模型如Elmore模型,等效Elmore模型和D2M模型。通过对几种模型的比较,表明,基于Weibull分布的RLC互连的统计延时模型是最精确的,和HSPICE相比,50%延时误差最大0.11%,蒙特卡洛分析中的均值和平均偏差误差最大2.02%。     

基于工艺波动下的互连延时统计模型

为了有效分析工艺波动对互连性能的影响,本文基于对数正态分布函数提出了一种RLC互连延时统计模型。在给定互连参数波动范围条件下,首先得到了电路矩的表达式,然后推导出了RLC互连延时均值和标准差。针对65nm和45nm的RLC互连树进行了验证,和HSPICE相比,采用本文方法计算得到的互连延时均值和标准差误差分别低于1%和5%。仿真表明本文方法具有足够的效率和精度。     

一种用于表征亚阈值电流镜电路中CMOS工艺波动的统计学方法

提出了一种新的表征亚阈值电路镜电路中CMOS工艺波动的方法.与现有的统计学方法相比,该方法在理论上和计算复杂度上相对简洁,但对亚阈值电流镜电路中的CMOS工艺波动做出了准确的评估.此模型利用统计学的概念将依赖于IC工艺的物理参数抽象为具有确定均值和方差的随机变量,并进一步将所有随机因素累加为离散鞅.在SMIC 0.18μm CMOS 1P6M混合信号工艺下,利用工作在100pA～1μA范围内、增益为100的亚阈值电流镜电路对此方法的正确性进行了实验验证.该理论成功地预测了～10%的实测芯片间工艺波动,并且给出了～1mV的片上阈值电压标准偏差,此结果与SMIC提供的没计参数吻合.该理论给出的概率分布与实测结果的偏差小于8%.同时,还针对高工艺稳定性的亚阈值模拟电路设计方法进行了相关的讨论.     

一种用于表征亚阈值电流镜电路中CMOS工艺波动的统计学方法

提出了一种新的表征亚阈值电路镜电路中CMOS工艺波动的方法.与现有的统计学方法相比,该方法在理论上和计算复杂度上相对简洁,但对亚阈值电流镜电路中的CMOS工艺波动做出了准确的评估.此模型利用统计学的概念将依赖于IC工艺的物理参数抽象为具有确定均值和方差的随机变量,并进一步将所有随机因素累加为离散鞅.在SMIC 0.18μm CMOS 1P6M混合信号工艺下,利用工作在100pA～1μA范围内、增益为100的亚阈值电流镜电路对此方法的正确性进行了实验验证.该理论成功地预测了～10%的实测芯片间工艺波动,并且给出了～1mV的片上阈值电压标准偏差,此结果与SMIC提供的没计参数吻合.该理论给出的概率分布与实测结果的偏差小于8%.同时,还针对高工艺稳定性的亚阈值模拟电路设计方法进行了相关的讨论.     

面向亚阈值的脉冲生成电路设计

基于SMIC 130nm工艺,提出了一种新的面向亚阈值的脉冲生成电路.设计中采用三输入与非门作为延时单元,更好地平衡单元的上拉延时和下拉延时,提高了延时路径的稳定性.新结构脉冲生成电路功能不受工艺偏差和温度变化的影响,在0.3V工作电压,不同工艺角以及-40~125℃温度范围内都能生成稳定可靠的脉冲信号.     

统计静态时序分析方法综述

随着纳米技术的进步，工艺参数波动给电路性能带来的不确定性愈发明显，成为影响集成电路设计的主要因素之一。为了对先进工艺下超大规模集成电路更准确地进行时序分析，现代计算机辅助设计工具通过概率分布来表征电路的时序行为，并提出了统计静态时序分析（Statistical static timing analysis,SSTA）的方法。为了提高SSTA的速度，各种各样的方法及模型被陆续提出来。本文对快速蒙特卡洛仿真法、离散数值法、查找表法、解析法这四类SSTA的加速方法展开研究并对其性能进行分析，介绍了SSTA最新的研究方向并对各种时序分析方法进行总结展望。     

一种考虑空间关联工艺偏差的统计静态时序分析方法

为了准确评估工艺参数偏差对电路延时的影响,该文提出一种考虑空间关联工艺偏差的统计静态时序分析方法。该方法采用一种考虑非高斯分布工艺参数的二阶延时模型,通过引入临时变量,将2维非线性模型降阶为1维线性模型;再通过计算到达时间的紧密度概率、均值、二阶矩、方差及敏感度系数,完成了非线性非高斯延时表达式的求和、求极大值操作。经ISCAS89电路集测试表明,与蒙特卡洛仿真(MC)相比,该方法对应延时分布的均值、标准差、5%延时点及95%延时点的平均相对误差分别为0.81%, -0.72%, 2.23%及-0.05%,而运行时间仅为蒙特卡洛仿真的0.21%,证明该方法具有较高的准确度和较快的运行速度。     

基于施密特触发的高鲁棒性亚阈值标准单元

亚阈值电路是低功耗重要发展方向之一。随着电源电压降低,晶圆代工厂提供的标准单元电路性能容易受噪声和工艺偏差的影响,已经成为制约亚阈值芯片的瓶颈。该文提出一种基于施密特触发(ST)与反向窄宽度效应(INWE)的亚阈值标准单元设计方案。该方案首先利用ST的迟滞效应与反馈机制,在电路堆叠结点处添加施密特反馈管以优化逻辑门、减少漏电流、增强鲁棒性;然后,采用INWE最小宽度尺寸与分指版图设计方法,提高电路的开关阈值与MOS管的驱动电流;最后,在TSMC 65 nm工艺下构建标准单元的物理库、逻辑库和时序库,完成测试验证。实验结果表明,所设计的亚阈值标准单元与文献相比,功耗降低7.2%～15.6%,噪声容限提升11.5%～15.3%,ISCAS测试电路的平均功耗降低15.8%。     

Analytical modeling of CMOS circuit delay distribution due to concurrent variations in multiple processes

A technique for modeling the effect of variations in multiple process parameters on circuit delay performance is proposed. The variation in saturation current I_on at the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. The delay of a two-input NAND gate with 65 nm gate length transistors is extensively characterized by mixed-mode simulations, which is then used as a library element. Appropriate templates for the NAND gate library are incorporated in a general purpose circuit simulator SEQUEL. A 4-bit × 4-bit Wallace tree multiplier circuit, consisting of two-input NAND gates is used to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, by generating delay distributions, using an extensive Monte Carlo analysis. The use of linear interpolation and linear superposition is evaluated to study simultaneous variations in two and more process parameters. An analytical model for gate delays, in terms of device drive current I_on, is proposed, which can be used to extend this methodology for a generic technology library with a variety of library elements. The model is validated against Monte Carlo simulations and is shown to have a typical error of less than 0.1% for simultaneous variations in multiple process parameters. The proposed methodology can be used for statistical timing analysis and circuit simulation at the gate level.     

一种基于机器学习的众工艺角延迟预测方法

在不同工艺角下,关键路径呈现显著差异,因此需要进行大量的静态时序分析,从而导致时序分析运行时间较长。与此同时,随着工艺尺寸的缩小,静态时序分析的精度问题变得不容忽视。本文提出一种基于机器学习的适用于众工艺角下的延迟预测方法,考虑工艺、电压和温度对时序的影响,利用基于自注意力Transformer模型对关键路径进行全局聚合编码,预测众工艺角下关键路径的统计延迟。在EPFL基准电路下进行验证,结果表明该方法的平均绝对误差范围为5.8%～9.4%,有良好的预测性能,可以提高时序分析的准确度和效率,进而缩短数字电路设计周期和设计成本。     

宽带延时宏模型高效延时提取方法

在高速电路信号完整性分析中,电大尺寸互连的建模仿真越来越普遍。而宽带延时宏模型以其仿真的高效性越来越受到重视,但现有延时提取方法比较耗时,限制了延时宏模型整体建模效率的提高。文中提出了一种基于傅里叶反变换IFT的高效延时提取方法。该方法不仅能从频域离散数据中提取多重延时项,而且可以较好地识别其中主要延时项以优化建模过程。文中在Matlab环境中实现该方法,并与目前常用的Gabor变换方法作对比。实验结果表明,文中方法大幅提高了延时提取效率,并且在宽带频域数据情况下具有较高的精度。     

基于亚阈值电流阵列的低成本物理不可克隆电路设计

物理不可克隆函数(PUF)能够提取出集成电路在加工过程中的工艺误差并将其转化为安全认证的密钥。由于常用于资源及功耗都受限的场合,实用化的PUF电路需要极高的硬件利用效率及较强的抗攻击性能。该文提出一种基于亚阈值电流阵列放电方案的低成本PUF电路设计方案。亚阈值电流阵列的电流具有极高的非线性特点,通过引入栅控开关和交叉耦合的结构,能够显著提升PUF电路的唯一性和稳定性。此外,通过引入亚阈值电流的设计可以极大地提高PUF的安全性,降低传统攻击手段的建模攻击。为了提升芯片的资源利用率,通过详细紧凑的版图设计和优化,该文提出的PUF单元面积仅为377.4 μm2,使得其特别适合物联网等低功耗低成本应用场景。仿真结果表明,该文所提亚阈值电路放电阵列PUF具有良好的唯一性和稳定性,无需校准电路的标准温度电压下唯一性为48.85%;在温度范围–20～80°C,电压变动范围为0.9～1.3V情况下,其可靠性达到了99.47%。     

基于工艺参数扰动的IC参数成品率多目标优化算法

在芯片制造工艺中,参数扰动影响了集成电路（Integrated Circuit,IC）成品率,使不同参数成品率间存在着此消彼长的相互制约关系,而目前IC参数成品率优化算法却主要局限于单一优化目标问题。本文提出一种基于工艺参数扰动的参数成品率多目标优化算法。该算法针对漏电功耗成品率及芯片时延成品率,首先构建具有随机相关性的漏电功耗及芯片时延统计模型;随后根据其相互制约特性建立基于切比雪夫仿射理论的参数成品率多目标优化模型;最后利用自适应加权求和得到分布均匀的帕雷托优化解。实验结果表明,该算法对于具有不同测试单元的实验电路均可求得大约30个分布均匀的帕雷托优化解,不仅能够有效权衡多个优化目标间的相互制约关系,还可以使传统加权求和优化方法在帕雷托曲线变化率较小之处得到优化解。     

High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell

The demand of low power high density integrated circuits is increasing in modern battery operated portable systems. Sub-threshold region of MOS transistors is the most desirable region for energy efficient circuit design. The operating ultra-low power supply voltage is the key design constraint with accurate output performance in sub-threshold region. Degrading of the performance metrics in Static random access memory (SRAM) cell with process variation effects are of major concern in sub-threshold region. In this paper, a bootstrapped driver circuit and a bootstrapped driver dynamic body biasing technique is proposed to assist write operation which improves the write-ability of sub-threshold 8T-SRAM cell under process variations. The bootstrapped driver circuit minimizes the write delay of SRAM cell. The bootstrapped driver dynamic body bias increases the output voltage levels by boosting factor therefore increasing in switching threshold voltage of MOS devices during hold and read operation of SRAM latch. The increment in threshold voltage improves the static noise margin and minimizing the process variation effects. Monte-Carlo simulation results with 3 \(\sigma \) Gaussian distributions show the improvements in write delay by 11.25 %, read SNM by 12.20 % and write SNM by 12.57 % in 8T-SRAM cell under process variations at 32 nm bulk CMOS process technology node.     

Extraction method for polycrystalline TFT above and below threshold model parameters

A procedure is presented to extract above and sub-threshold model parameters in polysilicon TFTs. It is based on the integration of the experimental data current, which has the advantage of reducing the effects of experimental noise. This method is applied to the linear and saturation regions for the above-threshold regime and allows the extraction of all the above-threshold and sub-threshold parameters. We already presented a unified extraction method for the above threshold parameters of a-Si:H and polysilicon TFTs, where the above-threshold regime the mobility is modeled as a function of the gate voltage to a power. An integration procedure is used to extract the device model parameters. In this paper, we complete the extraction procedure to cover all the device operation regions, that is the sub-threshold and above-threshold regimes. The extraction procedure provides in addition the possibility of monitoring the crystallization process of a-Si:H TFTs into polysilicon, which has become a widely used process of fabricating low temperature polysilicon TFTs. The process of polycrystallization manifests itself by a variation and change in sign of one of the model parameters. Extracted parameters can be correlated to input parameters required by AIM-Spice circuit simulator for device modeling. The accuracy of the simulated curves using the extracted parameters is verified with measurements.     

Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models

Interconnects constitute a dominant source of circuit delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this paper, a practical interconnect delay and slew analysis technique is presented to facilitate efficient evaluation of wire performance variability. By harnessing a collection of computationally efficient procedures and closed-form formulas, process variations are directly mapped into the variability of the output delay and slew. An efficient method based on sensitivity analysis is implemented to calculate driving point models under variations for gate-level timing analysis. The proposed adjoint technique not only provides statistical performance variations of the interconnect network under analysis, but also produces delay and slew expressions parameterized in the underlying process variations in a quadratic parametric form. As such, it can be harnessed to enable statistical timing analysis while considering important statistical correlations. Our experimental results have indicated that the presented analysis is accurate regardless of location of sink nodes and it is also robust over a wide range of process variations.     

An advanced diagnostic method for delay faults in combinational faulty circuits

Due to physical defects or process variations, a logic circuit may fail to operate at the desired clock speed. So, verifying the timing behavior of digital circuits is always necessary, and needs to test for delay faults. When a delay fault has been detected, a specific diagnostic method is required to locate the site of the fault in the circuit. So, a reliable method for delay fault diagnosis is proposed in this paper. Firstly, we present the basic diagnostic method for delay faults, which is based on multivalued simulation and critical path tracing. Next, heuristics are given that decrease the number of critical paths and improve diagnosis results. In the second part of this paper, we provide an approximate method to refine the results obtained with the basic diagnostic process. We compute the detection threshold of the potential delay faults, and use statistical studies to classify the faults from the most likely to be the cause of failure to the less likely. Finally, results obtained with ISCAS'85 circuits are presented to show the effectiveness of the method.