Floor acquisition multiple access (FAMA) in single‐channel wireless networks

The FAMANCS protocol is introduced for wireless LANs and adhoc networks that are based on a single channel and asynchronous transmissions (i.e., no time slotting). FAMANCS (for floor acquisition multiple access with nonpersistent carrier sensing) guarantees that a single sender is able to send data packets free of collisions to a given receiver at any given time. FAMANCS is based on a threeway handshake between sender and receiver in which the sender uses nonpersistent carrier sensing to transmit a requesttosend (RTS) and the receiver sends a cleartosend (CTS) that lasts much longer than the RTS to serve as a busy tone that forces all hidden nodes to back off long enough to allow a collisionfree data packet to arrive at the receiver. It is shown that carrier sensing is needed to support collisionfree transmissions in the presence of hidden terminals when nodes transmit RTSs asynchronously. The throughput of FAMANCS is analyzed for singlechannel networks with and without hidden terminals; the analysis shows that FAMANCS performs better than ALOHA, CSMA, and all prior proposals based on collision avoidance dialogues (e.g., MACA, MACAW, and IEEE 802.11 DFWMAC) in the presence of hidden terminals. Simulation experiments are used to confirm the analytical results.     

Noise considerations for mixed‐signal RF IC transceivers

This paper discusses design tradeoffs for mixedsignal radio frequency integrated circuit (RF IC) transceivers for wireless applications in terms of noise, signal power, receiver linearity, and gain. During air wave transmission, the signal is corrupted by channel noise, adjacent interfering users, image signals, and multipath fading. Furthermore, the receiver corrupts the incoming signal due to RF circuit nonlinearity (intermodulation), electronic device noise, and digital switching noise. This tutorial paper gives an overview of the design tradeoffs needed to minimize RF noise in an integrated wireless transceiver. Fundamental device noise and the coupling of switching noise from digital circuits to sensitive analog sections and their impact on RF circuits such as frequency synthesizers are examined. Methods to minimize mixedsignal noise coupling and to model substrate noise effects are presented.     

A scalable wireless virtual LAN

This paper presents a Wireless Virtual Local Area Network (WVLAN) to support mobility in IPoverATM local area networks. Mobility is handled by a joint ATMlayer handoff for connection rerouting and MAClayer handoff for location tracking, such that the effects of mobility are localized and transparent to the higherlayer protocols. Different functions, such as Address Resolution Protocol (ARP), mobile location, and ATM connection admission are combined to reduce protocol overhead and frontend delay for connectionless packet transmission in connectionoriented ATM networks. The proposed WVLAN, through the use of ATM technology, provides a scalable wireless virtual LAN solution for IP mobile hosts.     

Biasing a differential pair in low-voltage analog circuits: a systematic approach

This paper deals with a systematic approach to the common mode and the differential mode biasing of a differential transistor pair. Four different variants will be shown, two of these variants show practical importance; a practical circuit of one of these variants turns out to be the traditional long-tailed pair. This variant is mainly suited, if the input signal operates at voltage level, whereas another variant has great advantages if operation at current level occurs. Besides, the latter variant turns out to be very favorable in circuits operating with a single low supply voltage. Two practical circuits based on this variant are given.     

Scheduling and bandwidth allocation for the distribution of archived video in VOD systems

Providing costeffective videoondemand (VOD) services necessitates reducing the required bandwidth for transporting video over highspeed networks. In this paper, we investigate efficient schemes for transporting archived MPEGcoded video over a VOD distribution network. A video stream is characterized by a timevarying traffic envelope, which provides an upper bound on the bit rate. Using such envelopes, we show that video streams can be scheduled for transmission over the network such that the perstream allocated bandwidth is significantly less than the source peak rate. In a previous work [13], we investigated stream scheduling and bandwidth allocation using global traffic envelopes and homogeneous streams. In this paper, we generalize the scheduling scheme in [13] to include the heterogeneous case. We then investigate the allocation problem under windowbased traffic envelopes, which provide tight bounds on the bit rate. Using such envelopes, we introduce three streamscheduling schemes for multiplexing video connections at a server. The performance of these schemes is evaluated under static and dynamic scenarios. Our results indicate a significant reduction in the perstream allocated bandwidth when stream scheduling is used. While this reduction is obtained through statistical multiplexing, the transported streams are guaranteed stringent, deterministic quality of service (i.e., zero loss rate and small, bounded delay). In contrast to video smoothing, our approach requires virtually no buffer at the settop box since frames are delivered at their playback rate.     

The Complex Bootstrap Algorithm for Blind Separation of QAM Multiuser CDMA Signals

The bootstrap separator for multiuser signals is principally composed of cancelers, each one using the output of the other cancelers to facilitate control of its adaptive weight. In fact, such a structure performs as a signal separator rather than an interference canceler. Since for its separation there is no need for a reference signal (as in LMS cancelers), it is sometimes justifiably called a Blind Separator. However, for its operation the bootstrap separator requires a signal distinguisher termed discriminator. The algorithm was used in the past in applications such as dually polarized satellite communications and microwave terrestrial links. It was particularly reported for multiuser CDMA signal separating, with the signum function as discriminator. Especially for QAM signals, complex presentation is important. Therefore, we will concentrate in this report on what we call the Complex Bootstrap Algorithm. It is an extension to the previously reported bootstrap structure of [5]. We will examine its performance and emphasize the hardware saving in its implementation, and the ease of using it in simulation.     

Optical-LSP Establishment and a QoS Maintenance Scheme Based on Differentiated Optical QoS Classes in OVPNs

A virtual private network (VPN) over Internet has the benefit of being cost-effective and flexible. However, it has difficulties providing sufficient QoS and adequate transmission capacity for high bandwidth services. Given the increasing demand for high bandwidth Internet and the demand for QoS assurances in a VPN over Internet, IP/generalized multi-protocol label switching (GMPLS) based on a control plane combined with a high-bandwidth, dense-wavelength division multiplexing (DWDM) optical network is seen as a very favorable approach for realizing the future optical VPN (OVPN) over IP/GMPLS over DWDM. Within this architecture, providing QoS guaranteed multimedia services with a differentiated QoS guaranteed protocol framework with QoS recovery is one of the key issues to implement. Therefore, we suggest in this paper optical-label switched path (O-LSP) establishment and its QoS maintenance scheme based on differentiated optical QoS-service (DOQoS) classes. They are the key components for this DOQoS framework in assuring end-to-end QoS in an OVPN over IP/GMPLS over DWDM architecture.     

1 V All-MOS ΣΔ A/D Converters in the Log-domain

This paper presents novel low-voltage all-MOS analog circuit techniques for the synthesis of oversampling A/D converters. The new approach exploits the possibilities of Log-domain processing by using the MOSFET in subthreshold operation. Based on this strategy, a complete set of very low-voltage (down to 1 V) low-power (below 100 W) all-MOS basic building blocks is proposed. The resulting analog circuit techniques allow the integration of A/D converters for low-frequency (below 100 KHz) applications in digital CMOS technologies. Examples are given for a standard 0.35 m VLSI process.     

On minimum cost isolated failure immune networks

A telecommunications network is isolated failure immune (IFI) if and only if communication between operative sites can be completed as long as network failures are isolated. It is known that the class of minimal IFI networks is equivalent to the class of spanning 2-trees. To the best of our knowledge, this work is the first computational study dealing with the construction of a minimum cost IFI network. The problem is known to be NP-complete. We develop a tabu search based heuristic for solving the minimum cost spanning 2-tree (MCS2T) problem. The complex structure of 2-trees makes the tabu search heuristic highly dependent on the starting solution. We develop four heuristic algorithms to obtain diversified good starting solutions. They are: completion of a 2-tree from a spanning tree, two greedy approaches, and a method based on the recursive definition of a 2-tree. We also formulate an integer programming problem (IP) whose objective function value is a lower bound to the MCS2T problem. We solve the IP by developing a constraint generation scheme. The algorithms were tested on complete random graphs with Euclidean distances and on two real data sets (Civil Aeronautics Board) with instances of 10, 15, 20 and 25 nodes. As a result of this research for small problems (10 and 15 nodes), the heuristic solutions are on average within 0.8% from the optimal solution and for large problems (20 and 25 nodes), the average error is less than 2.8%.     

Predictive Caching Strategy for On-Demand Routing Protocols in Wireless Ad Hoc Networks

Route caching strategy is important in on-demand routing protocols in wireless ad hoc networks. While high routing overhead usually has a significant performance impact in low bandwidth wireless networks, a good route caching strategy can reduce routing overheads by making use of the available route information more efficiently. In this paper, we first study the effects of two cache schemes, link cache and path cache, on the performance of on-demand routing protocols through simulations based on the Dynamic Source Routing (DSR) protocol. Since the path cache DSR has been extensively studied, we focus in this paper on the link cache DSR in combination with timer-based stale link expiry mechanisms. The effects of different link lifetime values on the performance of routing protocol in terms of routing overhead, packet delivery ratio and packet latency are investigated. A caching strategy incorporating adaptive link timeout is then proposed, which aims at tracking the optimal link lifetime under various node mobility levels by adaptively adjusting the link lifetime based on the real link lifetime statistics. The performance of the proposed strategy is then compared with the conventional path cache DSR. The results show that without a timeout mechanism, a link cache scheme may suffer severe performance degradation due to the use of broken routes, while the proposed adaptive link cache strategy achieves significantly improved performance by reducing the routing overhead when the network traffic load is high.     

Current Operational Amplifier (COA): CMOS Realization and Active Compensation

A methodology for analysis and synthesis of lowpass sigma-delta () converters is presented in this paper. This method permits the synthesis of modulators employing continuous-time filters from discrete-time topologies. The analysis method is based on the discretization of a continuous-time model and using a discrete simulator, which is more efficient than an analog simulator. In our analysis approach, the influence of the sample and hold block and non-idealities of the feedback DAC can be systematically modeled by discrete-time systems. Finally, a realistic design of a second-order modulator with a compensation of the non-ideal behavior of the DAC is given. Moreover, simulation results show a good agreement with the theoretical predictions.     

Design and Analysis of On-Chip ESD Protection Circuit with Very Low Input Capacitance for High-Precision Analog Applications

An ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (m/m) in a 0.35-m silicided CMOS process, but it can sustain the human-body-model (machine-model) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only 1.0 pF (including the bond pad capacitance) for high-frequency applications. A design model to find the optimized layout dimensions and spacings on the input ESD clamp devices has been also developed to keep the total input capacitance almost constant (within 1% variation), even if the analog input signal has a dynamic range of 1 V.     

Economics of “design for test” to remain competitive in the 90s

This article emphasizes the criticality of maximizing value adders and minimizing the costs of design for test (DFT) in order to remain competitive in ASIC manufacturing in the 90s.     

Mobile ATM buffer capacity analysis

This paper extends a stochastic theory for buffer fill distribution for multiple on and off sources to a mobile environment. Queue fill distribution is described by a set of differential equations assuming sources alternate asynchronously between exponentially distributed periods in on and off states. This paper includes the probabilities that mobile sources have links to a given queue. The sources represent mobile user nodes, and the queue represents the capacity of a switch. This paper presents a method of analysis which uses mobile parameters such as speed, call rates per unit area, cell area, and call duration and determines queue fill distribution at the ATM cell level. The analytic results are compared with simulation results.This paper is partially funded by ARPA contract number J-FBI-94-223.The Mathematica code for this paper can be found on http://www.tisl.ukans.edu/sbush.     

Adaptive multicast routing in multirate loss networks

In this paper, we study two versions of the multicast routing problem in multirate loss networks: complete and partial. In the complete version of the multicast routing problem, the identities of all destination nodes are available to the multicast routing algorithm at once. Conversely, in the partial version of the multicast problem, the identities of the destination nodes are revealed to the routing algorithm one by one. Although the complete version of the multicast routing problem, also known as the Steiner tree problem, has been well studied in the literature, less attention has been paid for the definition of link costs and evaluating the performance of multicast routing algorithm from the network revenue point of view. Therefore, in this paper, we first propose two approaches, namely, the Markov Decision Processbased (MDPbased) and Least Loaded Routingbased (LLRbased) approaches, for defining link costs. Several heuristic multicast routing algorithms are then proposed for both fully connected networks and sparsely connected networks. We have also proposed a new performance metric, referred to as fractional reward loss, for evaluating the performance of multicast routing algorithms. Our simulation results indicate that algorithms based on partial destination information yield worse performance than those based on complete information. We also found that, for fully connected networks, algorithms that use LLRbased link costs yield very competitive performance as compared to those that use MDP approach. However, for sparsely connected networks, LLRbased algorithms yield significantly worse performance as compared to the MDPbased algorithms.     

The dangers of simplistic delay models

The identification of sensitizable paths and the determination of path delays play key roles in many delay fault testing schemes. In this paper we examine a range of gate delay models with respect to their impact on identifying both sensitizable paths and maximum circuit delays in combinational logic circuits. We provide recommendations on the minimum acceptable model for identifying critical paths, and a minimum acceptable model for determining maximum circuit delays. In particular, we recommend against the use of delay models which fail to distinguish between rise and fall delays. Such models, including the commonly-used unit-delay model, are shown to significantly misrepresent circuit delay behaviour, particularly with respect to critical paths and long false paths.This research is supported by the Natural Sciences and Engineering Research Council of Canada.     

Microsystems Engineering: A Great Stride Forward in Microelectronics Technology

The development of new-generation technological and engineering concepts by the example of microsystems technology and microsystems engineering approaches is considered.     

Simulation‐based performance evaluation of routing protocols for mobile ad hoc networks

In this paper we evaluate several routing protocols for mobile, wireless, ad hoc networks via packetlevel simulations. The ad hoc networks are multihop wireless networks with dynamically changing network connectivity owing to mobility. The protocol suite includes several routing protocols specifically designed for ad hoc routing, as well as more traditional protocols, such as link state and distance vector, used for dynamic networks. Performance is evaluated with respect to fraction of packets delivered, endtoend delay, and routing load for a given traffic and mobility model. Both small (30 nodes) and medium sized (60 nodes) networks are used. It is observed that the new generation of ondemand routing protocols use much lower routing load, especially with small number of peertopeer conversations. However, the traditional link state and distance vector protocols provide, in general, better packet delivery and endtoend delay performance.     

Quality Determination for Gate Delay Fault Tests Considering Three-State Elements

Most industrial digital circuits contain three-state elements besides pure logic gates. This paper presents a gate delay fault simulator for combinational circuits that can handle three-state elements like bus drivers, transmission gates and pulled busses. The well known delay faults--slow-to-rise and slow-to-fall--are considered as well as delayed transitions from isolating signal state high impedance to binary states 0 and 1 and vice versa. The presented parallel delay fault simulator distinguishes between non-robust, robust and hazard free tests and determines the quality of a test. Experimental results for ISCAS85/89 benchmark circuits are presented as well as results for industrial circuits containing three-state elements.