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1.
The EUBIONET III project has boosted (i) sustainable, transparent international biomass fuel trade, (ii) investments in best practice technologies and (iii) new services on biomass heat sector. Furthermore, it identified cost-efficient and value-adding use of biomass for energy and industry. The aims of this article are to provide a synthesis of the key results of this project. Estimated annual solid biomass potential in the EU-27 is almost 6600 PJ (157 Mtoe), of which 48% is currently utilised. The greatest potential for increased use lies in forest residues and herbaceous biomass. Trade barriers have been evaluated and some solutions suggested such as CN codes for wood pellets and price indexes for industrial wood pellets and wood chips. The analysis of wood pellet and wood chip prices revealed large difference amongst EU countries, but also that on the short term prices of woody and fossil fuels are barely correlated. Sustainable production and use of solid biomass are also deemed important by most European stakeholders, and many support the introduction of harmonised sustainability criteria, albeit under a number of preconditions. The study identified also that a number of woody and agro-industrial residue streams remain un- or underutilised. The estimated European total potential of agro-industrial sources is more than 250 PJ (7.2 Mtoe), the amount of unutilised woody biomass (the annual increment of growing stock) even amounts to 3150 PJ (75 Mtoe). Finally 35 case studies of biomass heating substituting fossil fuels were carried out, showing that the potential to reduce GHG emissions ranges between 90 and 98%, while costs are very similar to fossil fuel heating systems. Overall, we conclude that solid biomass is growing strongly, and is likely to heavily contribute to the EU renewable energy targets in the coming decade.  相似文献   
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Abstract

The asymptotic stability problem for a class of neutral systems with time‐varying delays and nonlinear uncertainties is investigated in this paper. LMI‐based delay‐dependent criteria are proposed to guarantee the asymptotic stability of the considered systems. New Lyapunov‐Krasovskii functional and Leibniz‐Newton formulae are used to find the delay‐dependent stability results. Finally, some numerical examples are illustrated to show the improved results from using this method.  相似文献   
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A new silicon controlled rectifier (SCR)-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance is proposed. The circuit function to detect positive or negative electrical transients during system-level electrostatic discharge (ESD) and electrical fast transient (EFT) tests has been verified in silicon chip. The experimental results in a 0.18-μm CMOS process have confirmed that the new proposed detection circuit can successfully memorize the occurrence of system-level electrical transient disturbance events. The detection results can be cooperated with firmware design to execute system recovery procedures, therefore the immunity of microelectronic systems against system-level ESD or EFT tests can be effectively improved.  相似文献   
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Abstract— An on‐panel delta—sigma analog‐to‐digital converter (ADC) has been implemented and verified for 3‐μm low‐temperature polysilicon (LTPS) technology with two basic blocks: a delta—sigma modulator and a decimation filter. From the experimental results, the digital output from the delta—sigma modulator is correctly matched with the analog input voltage ratio such that the digital output can be converted into 8‐bit digital code successfully under a supply voltage of 10 V from the decimation filter. The implemented on‐panel delta—sigma ADC can be used for the application of temperature‐to‐digital converter on glass substrate.  相似文献   
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A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide reliability problem in low-voltage CMOS process. The four-phase clocks were used to control the charge-transfer devices turning on and turning off alternately to suppress the return-back leakage current. A test chip has been implemented in a 65-nm CMOS process to verify the proposed charge pump circuit with four pumping stages. The measured output voltage is around 8.8 V with 1.8-V supply voltage to drive a capacitive output load, which is better than the conventional charge pump circuit with the same pumping stages. By reducing the return-back leakage current and without suffering gate-oxide overstress problem, the new proposed charge pump circuit is suitable for applications in low-voltage CMOS IC products.  相似文献   
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NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the desired ESD protection capability. All of them are usually based on a similar circuit scheme with multiple-stage inverters to drive the main ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage inverter and 1-stage inverter controlling circuits have been studied to verify the optimal circuit schemes in the NMOS-based power-rail ESD clamp circuits. Besides, the circuit performances among the main ESD clamp NMOS transistors drawn in different layout styles cooperated with the controlling circuit of 3-stage inverters or 1-stage inverter are compared. Among the NMOS-based power-rail ESD clamp circuits, an abnormal latch-on event has been observed under the EFT test and fast power-on condition. The root cause of this latch-on failure mechanism has been clearly explained by the emission microscope with InGaAs FPA detector.  相似文献   
10.
This paper presents a new electrostatic discharge (ESD) protection design for input/output (I/O) cells with embedded silicon-controlled rectifier (SCR) structure as power-rail ESD clamp device in a 130-nm CMOS process. Two new embedded SCR structures without latchup danger are proposed to be placed between the input (or output) pMOS and nMOS devices of the I/O cells. Furthermore, the turn-on efficiency of embedded SCR can be significantly increased by substrate-triggered technique. Experimental results have verified that the human-body-model (HBM) ESD level of this new proposed I/O cells can be greater than 5 kV in a 130-nm fully salicided CMOS process. By including the efficient power-rail ESD clamp device into each I/O cell, whole-chip ESD protection scheme can be successfully achieved within a small silicon area of the I/O cell.  相似文献   
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