Systematic and random variability analysis of two different 6T-SRAM layout topologies

This paper studies the device variability influence on 6T-SRAM cells in a function of the regularity level of their layout. Systematic and random variations have been analyzed when these memory circuits are implemented on a 45 nm technology node. The NBTI aging relevance on these cells has been also studied for two layout topologies and SNM has been seen as the parameter that suffers the highest impact with respect to cell aging and variability.     

A novel dynamic memory cell with internal voltage gain

A 2T1D dynamic memory cell with two transistors (T) and a gated diode (D) is presented. A gated diode is a two terminal MOS device in which charge is stored when a voltage above the threshold voltage is applied between the gate and the source, and negligible charge is stored otherwise. The gated diode acts as a nonlinear capacitance for voltage boosting, where voltage for 1-data is boosted high and voltage for 0-data stays low, achieving significant voltage gain of the internal stored voltage, higher signal margin, higher current drive and low-voltage memory operation. Details about the gated diode structure, its signal amplification, the memory cell circuits and the array structure, some hardware and test results are presented, followed by comparison to other memory cells and future directions.     

Characterization and 3D TCAD simulation of NOR-type flash non-volatile memories with emphasis on corner effects

The impact of 3D device architecture in aggressively scaled embedded non-volatile memories has been investigated by means of experiments and 3D TCAD simulations. A complete 3D calibration methodology covering DC and transient operating regimes has been introduced and validated against measurements for different technological options. This approach has been employed to determine the key features for device optimization. In particular, shallow trench isolation corners around the active area have been identified as critical regions of the memory cell for program and erase operations, as well as for gate coupling ratio optimization.     

2D TMD Channel Transistors with ZnO Nanowire Gate for Extended Nonvolatile Memory Applications

2D transition metal dichalcogenides (TMDs) have been extensively studied due to their excellent physical properties. Mixed dimensional devices including 2D materials have also been studied, motivated by the possibility of any synergy effect from unique structures. However, only few such studies have been conducted. Here, semiconducting 1D ZnO nanowires are used as thin gate material to support 2D TMD field effect transistors (FETs) and 2D stack‐based interface trap nonvolatile memory. For the trap memory, deep level electron traps formed at the first MoS₂/second MoS₂ stack interface are exploited, since the first MoS₂ is treated in an atomic layer deposition chamber for a short while. On the one hand, a complementary inverter type memory device can also be achieved using a long single ZnO wire as a common gate to simultaneously support both n‐ and p‐channel TMD FETs. In addition, it is found that the semiconducting ZnO nanowire itself operates as an n‐type channel when the TMD materials can become a top‐gate to charge the ZnO channel. It means that 2D (bottom gated) and 1D channel (top gated) FETs are respectively operational in a single device structure. The 1D–2D mixed devices seem deserving broad attention in both aspects of novelty and functionality.     

Scaling of multidielectric nonvolatile SONOS memory structures

Present-day low-power, portable lap-top computers and consumer products require non-volatile semiconductor memory (NVSM) operating at 5 V with a trend towards reducing this level to 3.3 V. The SONOS technology, an acronym for the polySilicon-blocking Oxide-Nitride-tunnel Oxide-Silicon structure used in capacitors and transistors, shows promise as a technology for present and future low voltage NVSM applications. The nitride layer in the dielectric sandwich permits the storage of charge resulting in adjustable threshold voltages. This paper examines the physics and characterization of scaled SONOS NVSM transistors in relation to reducing the programming voltage. We develop a model for the transient characteristics of the SONOS NVSM transistor with: (1) a simple closed-form solution valid for short programming times; and (2) a numerical solution covering the entire range of programming times. The simple closed-form solution clearly illustrates the dependence of the turn-on time and erase/white slope on the dielectric thicknesses, initial stored charge in the nitride, and programming voltage. In particular, we have examined: (1) decreasing the tunnel oxide thickness; and (2) scaling the blocking oxide thickness. By properly scaling the dielectric films (11 Å tunnel oxide, 50 Å nitride, 40 Å blocking oxide), a ±8 V programmable SONOS device has been obtained with a 50 μs write time and a 100 μs erase time for a 3 V memory window, and a ±5 V programmable device with a 100 ms erase and write time for a 1.5 V memory window.     

The thermal stability of one-transistor ferroelectric memory with Pt-Pb/sub 5/Ge/sub 3/O/sub 11/-Ir-poly-SiO/sub 2/-Si gate stack

The thermal stability of one-transistor ferroelectric nonvolatile memory devices with a gate stack of Pt-Pb/sub 5/Ge/sub 3/O/sub 11/-Ir-Poly-SiO/sub 2/-Si was characterized in the temperature range of -10/spl deg/C to 150/spl deg/C. The memory windows decrease when the temperatures are higher than 60/spl deg/C. The drain currents (I/sub D/) after programming to on state decrease with increasing temperature. The drain currents (I/sub D/) after programming to off state increase with increasing temperature. The ratio of drain current (I/sub D/) at on state to that at off state drops from 7.5 orders of magnitude to 3.5 orders of magnitude when the temperature increases from room temperature to 150/spl deg/C. On the other hand, the memory window and the ratio of I/sub D/(on)/I/sub D/(off) of the one-transistor memory device displays practically no change when the temperature is reduced from room temperature to -10/spl deg/C. One-transistor (1T) memory devices also show excellent thermal imprint properties. Retention properties of 1T memory devices degrade with increasing temperature over 60/spl deg/C.     

Root-Finding Methods for Assessing SRAM Stability in the Presence of Random Dopant Fluctuations

In this paper, we propose a closed-form method to evaluate the read stability of an SRAM cell via quartic root finding. By utilizing a simplified MOSFET device model, we model SRAM cell stability by a system of quartic equations. The algebraic nature of the equations along with simplified region boundaries provide the insight that only a few combinations of device operating regions correspond to the stability of the cell, instead of 729 combinations in the brute force approach. Such an insight not only makes it possible to have a quick “litmus test” to determine cell stability under variability but also significantly speeds up the analysis, compared to a traditional SPICE approach. Experimental results using industrial bulk CMOS models show that the results are in excellent agreement with SPICE results and 65X faster.      

3‐D optical modeling of thin‐film silicon solar cells on diffraction gratings

An effective rigorous 3‐D optical modeling of thin‐film silicon solar cells based on finite element method (FEM) is presented. The simulation of a flat single junction thin‐film silicon solar cell on thick glass (i.e., superstrate configuration) is used to validate a commercial FEM‐based package, the High Frequency Structure Simulator (HFSS). The results are compared with those of the reference software, Advanced Semiconductor Analysis (ASA) program, proving that the HFSS is capable of correctly handling glass as an incident material within very timely, short, and numerically stable calculations. By using the HFSS, we simulated single junction thin‐film silicon solar cells on glass substrates textured with one‐dimensional (1‐D) and two‐dimensional (2‐D) trapezoid‐shaped diffraction gratings. The correctness of the computed results, with respect to an actual device, is discussed, and the impact of different polarizations on spectral response and optical losses is examined. From the simulations carried out, optimal combinations for period and height in both 1‐D and 2‐D grating configurations can be indicated, leading to short‐circuit current percentage increase with respect to a flat cell of, respectively, 25.46% and 32.53%. With very limited computer memory usage and computational time in the order of tens of minutes for a single simulation, we promote the usage of 3‐D FEM as a rigorous and efficient way to simulate thin‐film silicon solar cells. Copyright © 2012 John Wiley & Sons, Ltd.     

Development of 3T eDRAM gain cells for enhancing read margin and data retention

This paper presents three transistors (3T) based Dynamic Random Access Memory (DRAM) cell in which noise, static power, and data retention voltage (DRV) have been reduced. The spesified parameters in the proposed eDRAM gain cell were improved by connecting the source of storage device to the read word line signal instead of supply voltage. As we all know, power consumption plays a vital role in VLSI design and thus, it is enumerated among the top challenges for the semiconductor chip industries. With the intention to maintain the performance of write operation, we diminish DRV and increase the read margin of eDRAM cell with our designed circuit which is introduced as “A Boosted 3T eDRAM gain cell”. It is a kind of eDRAM cell that utilizes a read word line (RWL) via three PMOS transistors instead of NMOS transistors. PMOS devices are preferred as they have radically less gate leakage current, which confer better results for data retention and thus, boost up the read margin of the cell. Simulation results have been obtained by using Cadence Virtuoso Tool at 45 nm technology for the proposed model. Based on simulation results we can conclude that the parameters of the proposed eDRAM gain cell essentially improved as compared with convertional eDRAM gain cell and the achieved parameters are as follows: static power is 0.767 pW, DRV is 142.009 mV and noise is 8.421 nV/Hz^1/2.     

Quantitative analysis and optimization techniques for on-chip cache leakage power

On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In nanometer-scale technology, the subthreshold leakage power is becoming one of the dominant total power consumption components of those caches. In this study, we present optimization techniques to reduce the subthreshold leakage power of on-chip caches assuming that there are multiple threshold voltages, V/sub T/'s, available. First, we show a cache leakage optimization technique that examines the tradeoff between access time and subthreshold leakage power by assigning distinct V/sub T/'s to each of the four main cache components-address bus drivers, data bus drivers, decoders, and static random access memory (SRAM) cell arrays with sense amplifiers. Second, we show optimization techniques to reduce the leakage power of L1 and L2 on-chip caches without affecting the average memory access time. The key results are: 1) two additional high V/sub T/'s are enough to minimize leakage in a single cache-3 V/sub T/'s if we include a nominal low V/sub T/ for microprocessor core logic; 2) if L1 size is fixed, increasing L2 size can result in much lower leakage without reducing average memory access time; 3) if L2 size is fixed, reducing L1 size may result in lower leakage without loss of the average memory access time for the SPEC2K benchmarks; and 4) smaller L1 and larger L2 caches than are typical in today's processors result in significant leakage and dynamic power reduction without affecting the average memory access time.     

A 0.4-μm 3.3-V 1T1C 4-Mb nonvolatile ferroelectric RAM withfixed bitline reference voltage scheme and data protection circuit

A 0.4-μm 3.3-V 1T1C 4-Mb nonvolatile ferroelectric random access memory (FRAM) was developed. The FRAM relies on the use of a reference scheme optimally adapted to the entire cell population of an individual device. A simple voltage level detector protects the device against data loss during drops in supply voltage. Finally, a special test mode was implemented to optimize read pulse width. By using these techniques, a high-performance 1T1C 4-Mb FRAM was successfully developed     

Uniform bipolar organic memory using vapor phase polymerized poly (3,4-ethylenedioxythiophene)

Organic memory device has emerged as an excellent candidate for the next generation storage devices due to its high performance and low production cost. In this paper, we report the fabrication and electrical characterization of an organic memory device made of vapor-phase polymerized PEDOT thin films that are highly uniform and free of PSS and free of unreacted reactants. The PEDOT memory device exhibited a typical bipolar resistive switching with a high ON/OFF current ratio of at least 10³, which was maintained for more than 10³ dc sweeping cycles. The device performance was stable for more than 10⁵ s. Moreover, the device containing 64 cells has very high cell to cell uniformity as demonstrated by (1) at least 93% of the cells displaying the ON/OFF current ratio of at least 10³ and (2) the deviation of the set and reset voltages from the average values being less than 0.5 V and 0.4 V, respectively. The maximum current before switching in the reset process was found to increase linearly with increase in the compliance current applied during the set process.     

Electrical characteristics of nano-crystal Si particles for nano-floating gate memory

In these days, the researches of non-volatile memory device using nano-crystal(NC)-Si are actively progressing to replace flash memory devices. Many kinds of non-volatile memory devices such as phase-change(P)-RAM, resistance(Re)-RAM, polymer(Po)-RAM, and nano-floating gate memory(NFGM) are being studied. In this work, we study NFGM device in which information is memorized by storing electrons in silicon nanocrystal. The NFGM device has shown great promise for ultra-dense high-endurance memory device for low-power applications [S. Tiwari, et al., Appl. Phys. Lett. 68 (1996) 1377], and it is able to fabricate 1T-type device. Thus, the NFGM is considered to replace existing flash memory device. Non-volatile memory device has been fabricated by using NC-Si particles. The NC-Si particles have broad size range of 1-5 nm and an average size of 2.7 nm, which are sufficiently small to indicate the quantum effect for silicon. The memory window has been analyzed by C-V characteristic of NC-Si particles. V_d-I_d and V_g-I_d characteristics of the fabricated device have also been measured.     

A 15 nm Ultra‐thin Body SOI CMOS Device' with Double Raised Source/Drain for 90 nm Analog Applications

Fully‐depleted silicon‐on‐insulator (FD‐SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the singleraised (SR) and double‐raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self‐heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self‐heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a 1.1 µm² 6T‐SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra‐thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.     

Nonvolatile Random Access Memory and Energy Storage Based on Antiferroelectric Like Hysteresis in ZrO2

To date antiferroelectrics have not been considered as nonvolatile memory elements because a removal of the external field causes a depolarization, resulting in a loss of the stored information. In comparison to ferroelectrics, antiferroelectrics are known for their enhanced fatigue resistance. Therefore, the main scope of this study is the development of a new memory device concept that would enable the usage of antiferroelectrics as a nonvolatile material with improved wake‐up and enhanced endurance properties. Recent studies have shown antiferroelectric behavior in ZrO₂, a material that is widely used in semiconductor industry, especially in dynamic random access memories. The basis of the new concept is the antiferroelectric hysteresis combined with the use of different workfunction electrodes that induce an internal bias field. Utilizing this approach, the field cycling endurance is drastically improved. Combining a comprehensive material study and electrical trap spectroscopy together with Landau–Ginzburg–Devonshire formalism, a proof of concept for a novel antiferroelectric random access memory is presented. For implementing a nonvolatile random access memory, the capacitors have to be realized in a 3D integrated version. These 3D integrated ZrO₂ capacitors can be used as energy storage devices as well, showing record high energy storage density and very high energy efficiency values.     

Memristive Logic‐in‐Memory Integrated Circuits for Energy‐Efficient Flexible Electronics

A memristive nonvolatile logic‐in‐memory circuit can provide a novel energy‐efficient computing architecture for battery‐powered flexible electronics. However, the cell‐to‐cell interference existing in the memristor crossbar array impedes both the reading process and parallel computing. Here, it is demonstrated that integration of an amorphous In‐Zn‐Sn‐O (a‐IZTO) semiconductor‐based selector (1S) device and a poly(1,3,5‐trivinyl‐1,3,5‐trimethyl cyclotrisiloxane) (pV3D3)‐based memristor (1M) on a flexible substrate can overcome these problems. The developed a‐IZTO‐based selector device, having a Pd/a‐IZTO/Pd structure, exhibits nonlinear current–voltage (I–V) characteristics with outstanding stability against electrical and mechanical stresses. Its underlying conduction mechanism is systematically determined via the temperature‐dependent I–V characteristics. The flexible one‐selector?one‐memristor (1S–1M) array exhibits reliable electrical characteristics and significant leakage current suppression. Furthermore, single‐instruction multiple‐data (SIMD), the foundation of parallel computing, is successfully implemented by performing NOT and NOR gates over multiple rows within the 1S–1M array. The results presented here will pave the way for development of a flexible nonvolatile logic‐in‐memory circuit for energy‐efficient flexible electronics.     

Stacked-nanowire device with virtual source/drain (SD-VSD) for 3D NAND flash memory application

A new stacked-nanowire device is proposed for 3-dimensional (3D) NAND flash memory application. Two single-crystalline Si nanowires are stacked in vertical direction using epitaxially grown SiGe/Si/SiGe/Si/SiGe layers on a Si substrate. Damascene gate process is adopted to make the gate-all-around (GAA) cell structure. Next to the gate, side-gate is made and device characteristics are controlled by the side-gate operations. By forming the virtual source/drain using the fringing field from the side-gate, short channel effect is effectively suppressed. Array design is also investigated for 3D NAND flash memory application.     

32 × 32 Crossbar Array Resistive Memory Composed of a Stacked Schottky Diode and Unipolar Resistive Memory

Various array types of 1‐diode and 1‐resistor stacked crossbar array (1D1R CA) devices composed of a Schottky diode (SD) (Pt/TiO₂/Ti/Pt) and a resistive switching (RS) memory cell (Pt/TiO₂/Pt) are fabricated and their performances are investigated. The unit cell of the 1D1R CA device shows high RS resistance ratio (≈10³ at 1.5 V) between low and high resistance state (LRS and HRS), and high rectification ratio (≈10⁵) between LRS and reverse‐state SD. It also shows a short RS time of <50 ns for SET (resistance transition from HRS to LRS), and ≈600 ns for RESET (resistance transition from LRS to HRS), as well as stable RS endurance and data retention characteristics. It is experimentally confirmed that the selected unit cell in HRS (logically the “off” state) is stably readable when it is surrounded by unselected LRS (logically the “on” state) cells, in an array of up to 32 × 32 cells. The SD, as a highly non‐linear resistor, appropriately controls the conducting path formation during the switching and protects the memory element from the noise during retention.     

铁电存储单元的设计和测试

基于被应用于实际设计之中的统一的铁电器件模型，详细讨论了２Ｔ ２Ｃ组态的铁电破坏性读出存储器单元的设计。在此基础上，设计和制造了分立元件的单元测试电路。通过与普通电容的对比实验，证实了铁电破坏性读出随机读取存储器与普通随机读取存储器不同的工作原理和模式。进而获得了被测ＦＲＡＭ单元的特性波形和铁电材料存储特性的有关数据。这些工作为进一步进行大规模铁电存储器的研究作了准备。     

An asynchronous GaAs MESFET static RAM using a new current mirrormemory cell

An experimental 1-kb GaAs MESFET static RAM using a new memory cell has been designed, fabricated and tested. The new memory cell is not subject to the destructive read problems that constrain the design of the conventional six-transistor memory cell. The biasing arrangement for this new cell minimizes the leakage currents associated with unselected bits attached to a column, maximizing the number of bits allowed per column. This new memory cell also provides a much larger access current for readout than is possible using a conventional memory cell of the same area and cell power. A write time of 1.0 ns and address access times of between 1.0 and 2.3 ns have been obtained from a 1-kb test circuit. A cell area of 350 μm² and cell current of 60 μA were achieved using a conventional E/D process