I-V characteristics of a methanol sensor for direct methanol fuel cell (DMFC) as a function of deposited platinum (Pt) thickness

We have fabricated methanol sensor for monitoring the methanol concentration in direct methanol fuel cells. A thin composite nafion membrane was used as an electrolyte. We have analyzed the I-V characteristic of the fabricated methanol sensor as functions of methanol concentration, catalyst electrode and platinum (Pt) thickness. When we measured the sensor with 10 nm Pt and at 1 V, the current value was 1.30×10⁻⁶, 1.96×10⁻⁶, and 2.80×10⁻⁶ A for three methanol concentration of 1, 2, and 3 M, respectively. And when the methanol concentration was fixed at 2 M, the current value of the fabricated device with Pt of 5, 10 and 15 nm was 3.06×10⁻⁶, 1.96×10⁻⁶, and 1.00×10⁻⁶ A, respectively.     

Analysis of interface states and series resistance of MIS Schottky diodes using the current-voltage (I-V) characteristics

The purpose of this paper is to analyze interface states in Al/SiO₂/p-Si (MIS) Schottky diodes and determine the effect of SiO₂ surface preparation on the interface state energy distribution. The current-voltage (I-V) characteristics of MIS Schottky diodes were measured at room temperature. From the I-V characteristics of the MIS Schottky diode, ideality factor (n) and barrier height (Φ_B) values of 1.537 and 0.763 eV, respectively, were obtained from a forward bias I-V plot. In addition, the density of interface states (N_ss) as a function of (E_ss-E_v) was extracted from the forward bias I-V measurements by taking into account both the bias dependence of the effective barrier height (Φ_e), n and R_s for the MIS Schottky diode. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. In addition, the values of series resistance (R_s) were determined using Cheung’s method. The I-V characteristics confirmed that the distribution of N_ss, R_s and interfacial insulator layer are important parameters that influence the electrical characteristics of MIS Schottky diodes.     

Fabrication and characterization of p-n junctions based on ZnO and CuPc

p-n Junctions based on zinc oxide (ZnO) and copper-phthalocyanine (CuPc) were fabricated using pulsed laser deposition and thermal evaporator techniques, respectively. Current-voltage (I-V) characteristics of the ZnO-CuPc junction showed rectifying behavior. Various junction parameters such as barrier height and ideality factor were calculated using I-V data and observed to be 0.63 ± 0.02 eV and 4.0 ± 0.3, respectively. Cheung and Norde’s method were used to compare the junction parameters obtained by I-V characteristics.     

Thermal and plasma enhanced atomic layer deposition ruthenium and electrical characterization as a metal electrode

Ruthenium thin films were grown by thermal and plasma-enhanced atomic layer deposition (PE-ALD) using O₂ and ammonia (NH₃) plasma, respectively. RuCp₂ and Ru(EtCp)₂ were used as Ru precursors. Pure and low resistivity (<20 μΩ cm) Ru films were grown by PE-ALD as well as thermal ALD. PE-ALD Ru showed no nucleation delay on various substrates including TaN_x, Si, and SiO₂, in contrast to thermal ALD Ru. And the root-mean-square (RMS) roughness of PE-ALD Ru was lower than that of thermal ALD Ru. Additionally, metal-oxide-semiconductor (MOS) capacitor composed of p-Si/ALD Ta₂O₅/ALD Ru (35 nm) was fabricated and C-V measurements were performed for as-deposited sample. Very small hysteresis of 20 mV was obtained, and effective work function difference to Si substrate was minimal as −0.03 V. For comparison, MOS capacitor was fabricated using sputtered Ru and large hysteresis of 0.5 V and flat band voltage (V_FB) shift to negative value were observed. This result indicates that ALD process produces more reliable, damage free Ru gate compared to sputtering process.     

Ultrathin insulating silica layers prepared from adsorbed TEOS, H2O and NH3 as a catalyst

Homogeneous ultrathin silica films were deposited without need of any expensive equipment and high-temperature processes (t?200 °C). Repeated adsorption of tetraethoxysilane (TEOS) multimolecular layers and their subsequent reaction with H₂O/NH₃ mixed vapours at atmospheric pressure and room temperature were used. By preparing the Al/SiO₂/N-Si MOS structure conditions were attained for electrical characterisation of the thin oxide layer by capacitance (C-V) and current (I-V) measurements. These measurements confirmed acceptable insulating properties of the oxide, the maximum breakdown field intensity being E_bd=5.4 MV/cm. The total defect charge of the MOS structure was positive, affected by a high trap density at the Si-SiO₂ interface.     

Visible blind p-i-n ultraviolet photodetector fabricated on 4H-SiC

The 4H-SiC visible blind p-i-n ultraviolet (UV) photodetector has been designed, fabricated and characterized. The dark I-V characteristics of the detector were carried out at room temperature. It was found that the photocurrent of detector was at least two orders of magnitude higher than the dark current. The photon response spectrum of the detector was measured and calibrated. The ratio of responsivity at 275 nm to that at 375 nm was nearly 100, which implied that the photodetector has a great improved visible blind performance.     

On the temperature dependence of series resistance and interface states in Al/SiO2/p-Si (MIS) Schottky diodes

The capacitance-voltage-temperature (C-V-T) and conductance-voltage-temperature (G/w-V-T) characteristics of metal-semiconductor (Al/p-Si) Schottky diodes with thermal growth interfacial layer were investigated by considering series resistance effect in the wide temperature range (80-400 K). It is found that in the presence of series resistance, the forward bias C-V plots exhibit a peak, and experimentally shows that the peak positions shift towards higher positive voltages with increasing temperature, and the peak value of the capacitance has a maximum at 80 K. The C-V and (G/w-V) characteristics confirm that the N_ss and R_s of the diode are important parameters that strongly influence the electric parameters in (Al/SiO₂/p-Si) MIS Schottky diodes. The crossing of the G/w-V curves appears as an abnormality when seen with respect to the conventional behaviour of the ideal MS or MIS Schottky diode. It is thought that the presence of a series resistance keeps this intersection hidden and unobservable in homogeneous Schottky diodes, but it appears in the case of inhomogeneous Schottky diode. In addition, the high frequency (C_m) and conductance (G_m/w) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance.     

Electrical properties of metal-ferroelectric-insulator-semiconductor structure using BaxSr1−xTiO3 for ferroelectric-gate field effect transistor

Perovskite ferroelectric Ba_xSr_1−xTiO₃ (x = 0.5, 0.6, 0.7 and 0.8) thin films have been fabricated as metal-ferroelectric-insulator-semiconductor (MFIS) configurations using a sol-gel technique. The C-V characteristics for different Ba-Sr ratios and different film thicknesses have been measured in order to investigate the ferroelectric memory window effect. The results show that the memory window width increases with the increase both of Ba content and film thickness. This behavior is attributed to the grain size and dipole dynamics effect. It is found also that the memory window increases as the applied voltage increases. In addition, the leakage current density for the films is measured and it is found to be of the order of 10⁻⁸ A/cm² for all tested samples, indicating that the films have good insulating characteristics.     

The protective effect of thin amorphous hydrogenated carbon a-C:H films during metallisation of metal-carbon-oxide-silicon (MCOS) diodes

Capacitance-voltage (C-V) characteristics of the as-grown metal(Al)-carbon-oxide(SiO₂)-semiconductor(Si) structures are examined at the frequency of 1 MHz and compared with the C-V characteristics of the conventional metal(Al)-SiO₂-Si (MOS) structures. The density of the oxide charge Q_o/q is extracted from the experimental results. Q_o/q was found to be 1×10¹² cm⁻² for the MOS structures and 7×10¹¹ cm⁻² for the metal-carbon-oxide-silicon structures. This difference can be attributed to the presence of the carbon layer which acts as a protective coating during metallisation of the wafers.     

Extraction of electronic parameters of Schottky diode based on an organic Orcein

An Au/Orcein/p-Si/Al device was fabricated and the current-voltage measurements of the devices showed diode characteristics. Then the current-voltage (I-V), capacitance-voltage (C-V) and capacitance-frequency (C-f) characteristics of the device were investigated at room temperature. Some junction parameters of the device such as ideality factor, barrier height, and series resistance were determined from I-V and C-V characteristics. The ideality factor of 2.48 and barrier height of 0.70 eV were calculated using I-V characteristics. It has been seen that the Orcein layer increases the effective barrier height of the structure since this layer creates the physical barrier between the Au and the p-Si. The interface state density N_ss were determined from the I-V plots. The capacitance measurements were determined as a function of voltage and frequency. It was seen that the values of capacitance have modified with bias and frequency.     

Printed,Flexible, Organic Nano‐Floating‐Gate Memory: Effects of Metal Nanoparticles and Blocking Dielectrics on Memory Characteristics

The effects of using a blocking dielectric layer and metal nanoparticles (NPs) as charge‐trapping sites on the characteristics of organic nano‐floating‐gate memory (NFGM) devices are investigated. High‐performance NFGM devices are fabricated using the n‐type polymer semiconductor, poly{[N,N′‐bis(2‐octyldodecyl)‐naphthalene‐1,4,5,8‐bis(dicarboximide)‐2,6‐diyl]‐alt‐5,5′‐(2,2′‐bithiophene)} (P(NDI2OD‐T2)), and various metal NPs. These NPs are embedded within bilayers of various polymer dielectrics (polystyrene (PS)/poly(4‐vinyl phenol) (PVP) and PS/poly(methyl methacrylate) (PMMA)). The P(NDI2OD‐T2) organic field‐effect transistor (OFET)‐based NFGM devices exhibit high electron mobilities (0.4–0.5 cm² V^?1 s^?1) and reliable non‐volatile memory characteristics, which include a wide memory window (≈52 V), a high on/off‐current ratio (I_on/I_off ≈ 10⁵), and a long extrapolated retention time (>10⁷ s), depending on the choice of the blocking dielectric (PVP or PMMA) and the metal (Au, Ag, Cu, or Al) NPs. The best memory characteristics are achieved in the ones fabricated using PMMA and Au or Ag NPs. The NFGM devices with PMMA and spatially well‐distributed Cu NPs show quasi‐permanent retention characteristics. An inkjet‐printed flexible P(NDI2OD‐T2) 256‐bit transistor memory array (16 × 16 transistors) with Au‐NPs on a polyethylene naphthalate substrate is also fabricated. These memory devices in array exhibit a high I_on/I_off (≈10^{4 ± 0.85}), wide memory window (≈43.5 V ± 8.3 V), and a high degree of reliability.     

Titanium-aluminum oxynitride (TAON) as high-k gate dielectric for sub-32 nm CMOS technology

High-k insulators for the next generation (sub-32 nm CMOS (complementary metal-oxide-semiconductor) technology), such as titanium-aluminum oxynitride (TAON) and titanium-aluminum oxide (TAO), have been obtained by Ti/Al e-beam evaporation, with additional electron cyclotron resonance (ECR) plasma oxynitridation and oxidation on Si substrates, respectively. Physical thickness values between 5.7 and 6.3 nm were determined by ellipsometry. These films were used as gate insulators in MOS capacitors fabricated with Al electrodes, and they were used to obtain capacitance-voltage (C-V) measurements. A relative dielectric constant of 3.9 was adopted to extract the equivalent oxide thickness (EOT) of films from C-V curves under strong accumulation condition, resulting in values between 1.5 and 1.1 nm, and effective charge densities of about 10¹¹ cm⁻². Because of these results, nMOSFETs with Al gate electrode and TAON gate dielectric were fabricated and characterized by current-voltage (I-V) curves. From these nMOSFETs electrical characteristics, a sub-threshold slope of 80 mV/dec and an EOT of 0.87 nm were obtained. These results indicate that the obtained TAON film is a suitable gate insulator for the next generation (MOS) devices.     

A study on the improved performances of OLED using CMP process parameters determined by DOE method

In order to study the chemical-mechanical polishing (CMP) characteristics of indium-tin oxide (ITO) thin film with a sufficient removal amount and a good planarity, the optimal CMP process conditions were determined by using a design of experiment (DOE) approach. The electrical and optical properties, such as current-voltage (I-V) curve and photoluminescence spectrum, were discussed in order to evaluate the possibility of the CMP application for an organic light emitting diode (OLED) device using an ITO film. The electrical I-V characteristics and optical properties of ITO thin film were improved after the CMP process using optimized process conditions compared to that of as-deposited thin film before the CMP process.     

Fabrication of Bistable Switching Memory Devices Utilizing Polymer–ZnO Nanocomposites

This work reports fabrication of bistable memory switching devices employing wet-chemically synthesized ZnO nanoparticles with polymethyl methacrylate and poly[2-methoxy-5-(2-ethylhexyloxy)-1,4-phenylenevinylene] polymers. ZnO nanoparticle-embedded polymer layers were coated on conducting indium tin oxide (ITO) glasses using the spin-coating technique. Synthesized ZnO nanoparticles were characterized by scanning electron microscopy, transmission electron microscopy, x-ray diffraction, energy-dispersive x-ray, and photoluminescence studies. These ZnO particles are 20?nm to 30?nm in size with hexagonal structure. Switching and memory effects of the devices fabricated employing the ZnO nanoparticle?Cpolymer composite films were investigated using current?Cvoltage (I?CV) characteristics. The I?CV measurements of both polymer devices showed electrical bistability. The ON to OFF current ratio of the bistable device was found to be ??10³. The observed current?Ctime response showed good memory retention behavior of the fabricated devices. The carrier transport mechanism of the devices has been described on the basis of I?CV experimental results and electronic structure.     

Effects of active area and gate doping method on program threshold voltage in an EEPROM cell

In this paper, we investigate dependency of program threshold voltage (V_T) in EEPROM cell on active area and doping method of floating gate. With in situ doped floating gate, it is found that there is a sharp drop of program V_T from 4 to 2.25 V when the channel width is reduced from 0.30 to 0.22 μm, while doping by ion implantation results in slight reduction of program V_T from 3.95 to 3.69 V. It also appears that channel length is another critical factor to affect on reduction of program V_T. In case of in situ doped floating gate, the program V_T is reduced from 3.9 to 2.7 V when the channel length is reduced from 0.20 to 0.18 μm. TEM analysis reveals that thermal oxidation in tunnel oxide region occurs during subsequent high temperature oxidation due to oxidant penetration via interface of silicon surface and sidewall silicon nitride.     

Negative capacitance peculiarities in a-Si:H/c-Si rectifier structure

Nontrivial negative capacitance (NC) effect, observed in a-Si:H/c-Si heterostructure devices, is discussed emphasizing the theoretical interpretation of experimental data. To explain NC effect, we have performed dark current voltage (I-V) and admittance measurements (C-V, G-V, C-f and G-f). The calculated values of series resistance (R_s) and barrier height (Φ_Bo) have the values from 100 to 114.7 Ω and 0.94 to 0.83 eV, respectively. Also, below 50% helium dilution rate, diode ideality factor (n) becomes bigger than 2, because tunneling at junction interface plays a major role. The measured room temperature (294 K) dark I-V result has been used during the fitting process for suggested capacitance model (Eq. (18)). The measured NC values exhibit strongly voltage depended behavior. This unexpected behavior is attributed to the presence of inductively coupled space charge region which might possibly be stemmed from the helium diluted a-Si:H material. It is seen that the measured NC values are well fitted with suggested capacitance model (Eq. (18)). Application of suggested correction formula on to experimental C-V data yields satisfactory results. It is shown that the calculated inductance values of the investigated device range from 10 to 42 μH and after correction, NC values are no longer observed in the C_d-V data.     

Charging effects in CdSe nanocrystals embedded in SiO2 matrix produced by rf magnetron sputtering

Charging effects in CdSe nanocrystals embedded in SiO₂ matrix fabricated by rf magnetron co-sputtering technique were electrically characterized by means of capacitance-voltage (C-V) combined with current-voltage (I-V). The presence of CdSe nanocrystals was demonstrated by X-ray diffraction technique. The average size of nanocrystals was found to be approximately 3 nm. The carriers transport in the CdSe/SiO₂ structure was shown to be a combination of Fowler-Nordheim tunnelling and Poole-Frenkel mechanisms. A memory effect was demonstrated and a retention time was measured.     

Investigation of field-effect transistors fabricated by metal-ion-doped nano-titania using sol-gel technique

In our present investigations, field-effect transistors (FETs) based on nano-TiO₂ and metal-ion-doped TiO₂ particles were fabricated and their characteristics were studied. Semiconductor characteristics of nano-TiO₂/metal-ion-doped TiO₂ films, which perform as a diode, were used in the fabrication of the FET device. The performance of the FET device was evaluated by analyzing the data obtained from source-drain current vs. voltage (I_ds-V_ds) by controlling the gate voltage (V_g). The on/off conditions of the transistor were feasibly performed and the threshold voltage (V_t) were determined by adjusting V_g for different types of the FET design. In addition, the influential factors, such as type of metal ions, and positions of TiO₂ and metal-ion-doped TiO₂ layers, on the performance of the FET device were also discussed in this study.     

A FinFET memory with remote carrier trapping in ONO buried insulator

Advanced FinFETs fabricated on SiO₂-Si₃N₄-SiO₂ (ONO) buried insulator are investigated for flash memory applications. Systematic measurements reveal that the Si₃N₄ layer can easily trap charges by applying appropriate drain bias. The amount of trapped/detrapped charges in the buried nitride is sensed remotely by gate coupling through the variation of the drain current flowing at the front-gate interface. The front-channel threshold voltage variation, ΔV_THF, resulting from the charge trapping, induces a hysteresis “window” proper to non-volatile memory devices. Finally, our measurements highlight the geometrical parameter effects on the memory window size.     

The effects of active layer thickness on Programmable Metallization Cell based on Ag–Ge–S

Programmable Metallization Cell (PMC) is a newly developed non-volatile memory device based on chalcogenide solid electrolytes. In this paper, we studied the PMC’s electrical properties as a function of its active layer thickness. The PMC devices are fabricated based on Ag-Ge-S materials using thermal evaporation method. The fabricated devices have their active layer thickness ranges from 8 nm to 30 nm. The I-V characteristics of the fabricated devices are studied as a function of their active layer thickness. It is observed that the ‘ON’ resistance of PMC displays a decreasing trend as we increase the active layer thickness. This is because less deposition nuclei can be formed on the cathode/electrolyte interface in thinner devices, which limits the number of conduction links that can be formed. The SET voltage also decreases slightly as increase of the active layer thickness. This is probably because thinner Ag-Ge-S layer localizes Ag ions’ movements due to the large size of Ag+ ion. On the other hand, the RESET voltage increases as we increase the active layer thickness, which is because there are more conduction links to be ionized in thicker devices.