pnp型SiGe HBT的制备研究

从pnp型Si/SiGe HBT的能带结构出发，阐述pnp型Si/SiGe HBT的较大原理，采用MBE方法生长Si/Si1-xGex合金材料，并对Si/Si1-xGex合金材料的物理特性和异质结特性进行表征，在重庆固体电子研究所工艺线上，研制出了pnp型Si/SiGe HBT器件，器件参数为：Vcb0=9V,Vcc0=2.5V,Veb0=5V,β＝10。     

TiN栅薄膜全耗尽SOI CMOS器件

制备并研究了TiN栅薄膜全耗尽SOI CMOS器件,并对其关键工艺进行了详细阐述.相对于双多晶硅栅器件,在不改变阈值电压的前提下,可以减小nMOS和pMOS的沟道掺杂浓度,进而提高迁移率.由于TiN的功函数处于中间禁带,在几乎相同的调整阈值注入剂量下,可以得到对称的阈值电压.当顶层硅膜厚度减小时,可以改善短沟道效应.     

绝缘层上Si/应变Si1-xGex/Si异质结p-MOSFET电学特性二维数值分析

对绝缘层上Si/应变Si1-xGex/Si异质结p-MOSFET电学特性进行二维数值分析,研究了该器件的阈值电压特性、转移特性、输出特性.模拟结果表明,随着应变Si1-xGex沟道层中的Ge组分增大,器件的阈值电压向正方向偏移,转移特性增强;当偏置条件一定时,漏源电流的增长幅度随着Ge组分的增大而减小;器件的输出特性呈现出较为明显的扭结现象.     

多晶发射极双台面微波功率SiGe HBT

研制成功了可商业化的75mm单片超高真空化学气相淀积锗硅外延设备SGE50 0 ,并生长了器件级SiGeHBT材料.研制了具有优良小电流特性的多晶发射极双台面微波功率SiGeHBT器件,其性能为:β=60 @VCE/IC=9V/ 30 0 μA ,β=1 0 0 @5V/ 50mA ,BVCBO=2 2V ,ft/ fmax=5 4GHz/ 7 7GHz @1 0指,3V/ 1 0mA .多晶发射极可进一步提供直流和射频性能的折衷,该工艺总共只有6步光刻,与CMOS工艺兼容且(因多晶发射极)无需发射极外延层的生长,这些优点使其适合于商业化生产.利用60指和1 2 0指的SiGeHBT制作了微波锗硅功率放大器.60指功放在90 0MHz和3 5V/ 0 2A偏置时在1dB压缩     

多晶发射极双台面微波功率SiGe HBT

研制成功了可商业化的75mm单片超高真空化学气相淀积锗硅外延设备SGE500,并生长了器件级SiGe HBT材料.研制了具有优良小电流特性的多晶发射极双台面微波功率SiGe HBT器件,其性能为:β=60@VCE/IC=9V/300μA,β=100@5V/50mA,BVCBO=22V,ft/fmax=5.4GHz/7.7GHz@10指,3V/10mA.多晶发射极可进一步提供直流和射频性能的折衷,该工艺总共只有6步光刻,与CMOS工艺兼容且(因多晶发射极)无需发射极外延层的生长,这些优点使其适合于商业化生产.利用60指和120指的SiGe HBT制作了微波锗硅功率放大器.60指功放在900MHz和3.5V/0.2A偏置时在1dB压缩点给出P1dB/Gp/PAE＝22dBm/11dB/26.1%.120指功放900MHz工作时给出了Pout/Gp/PAE＝33.3dBm (2.1W)/10.3dB/33.9%@11V/0.52A.     

用于HBT的SiGe合金材料层的腐蚀工艺研究

探索利用反应离子刻蚀(RIE)和湿法腐蚀Si1-xGex合金材料的工艺条件.对两种腐蚀方法的利弊进行了对比,找出腐蚀Si1-xGex合金材料的实用化途径,并且解决了不同Ge含量的Si1-xGex合金材料的腐蚀速度控制.     

UHV/CVD生长SiGe/Si异质结构材料

以Si2H6和GeH4作为源气体,用UHV/CVD方法在Si(100)衬底上生长了Sil-xGex合金材料和Si1-xGex/Si多量子阱结构.用原子力显微镜、X光双晶衍射和透射电子显微镜对样品的表面形貌、均匀性、晶格质量、界面质量等进行了研究.结果表明样品的表面平整光滑,平均粗糙度为1.2nm;整个外延片各处的晶体质量都比较好,各处生长速率平均偏差为3.31％,合金组分x值的平均偏差为2.01％;Si1-xGex/Si多量子阱材料的X光双晶衍射曲线中不仅存在多级卫星峰,而且在卫星峰之间观察到了Pendellosung条纹,表明晶格质量和界面质量都很好;Si1-xGex/Si多量子阱材料的TEM照片中观察不到位错的存在.     

3C-SiC/Si异质结二极管的高温特性

研究了低压化学气相淀积方法制备的n- 3C- Si C/p- Si(10 0 )异质结二极管(HJD)在30 0～4 80 K高温下的电流密度-电压(J- V)特性.室温下HJD的正反向整流比(通常定义为±1V外加偏压下)最高可达1.8×10 4 ,在4 80 K时仍存在较小整流特性,整流比减小至3.1.在30 0 K温度下反向击穿电压最高可达2 2 0 V .电容-电压特性表明该Si C/Si异质结为突变结,内建电势Vbi为0 .75 V.采用了一个含多个参数的方程式对不同温度下异质结二极管的正向J-V实验曲线进行了很好的拟和与说明,并讨论了电流输运机制.该异质结构可用于制备高质量异质结器件,如宽带隙发射极Si C/Si HBT     

TiN栅及抬高源漏的薄膜全耗尽SOI CMOS器件的模拟研究

对0．25μm TiN栅及抬高源漏的薄膜全耗尽SOI CMOS器件进行了模拟研究。由于TiN栅具有中间禁带功函数，在低的工作电压下，NMOS和PMOS的阈值电压都得到了优化。随硅膜厚度的减小，釆用源漏抬高结构，减小了源漏串联电阻。采用抬高源漏结构的NMOS和PMOS，其饱和电流分别提高了36％和41％。由于采用源漏抬高能进一步降低硅膜厚度，短沟道效应也得到了抑制．     

双应变SiGe/Si异质结CMOS的设计及其电学特性的Medici模拟

本文提出一种沟道长度为0.125 μm的异质结CMOS(HCMOS)器件结构.在该结构中,压应变的SiGe与张应变的Si分别作为异质结PMOS(HPMOS)与异质结NMOS(HNMOS)的沟道材料,且HPMOS与HNMOS为垂直层叠结构;为了精确地模拟该器件的电学特性,修正了应变SiGe与应变Si的空穴与电子的迁移率模型;利用Medici软件对该器件的直流与交流特性,以及输入输出特性进行了模拟与分析.模拟结果表明,相对于体Si CMOS器件,该器件具有更好的电学特性,正确的逻辑功能,且具有更短的延迟时间,同时,采用垂直层叠的结构此类器件还可节省约50%的版图面积,有利于电路的进一步集成.     

1.55μmSi_(1-x)Ge_x/Si光开关与光探测器集成的分析及设计

对１．５５μｍ波长的Ｓｉ１－ｘＧｅｘ光波导开关和Ｓｉ１－ｘＧｅｘ／Ｓｉ红外探测器的集成结构进行了系统的理论分析和优化设计。设计结果为：（１）对Ｓｉ１－ｘＧｅｘ光开关，Ｇｅ含量ｘ＝０．０５，波导的内脊高、脊宽和腐蚀深度分别为３，８．５和２．６μｍ，分支角为５～６°。要实现对１．５５μｍ波长光的开关作用，ｐｎ＋结上所需加的正向偏压值应为０．９７Ｖ；（２）对Ｓｉ１－ｘＧｅｘ／Ｓｉ探测器，Ｇｅ含量ｘ＝０．５，探测器由２３个周期的６ｎｍＳｉ０．５Ｇｅ０．５和１７ｎｍＳｉ交替组成厚度为５５０ｎｍ，长度约为１．５～２ｍｍ的超晶格，内量子效率达８０％以上。     

基于应变Si/SiGe的CMOS电特性模拟研究

提出了一种应变Si/SiGe异质结CMOS结构,采用张应变Si作n-MOSFET沟道,压应变SiGe作p-MOSFET沟道,n-MOSFET与p-MOSFET采用垂直层叠结构,二者共用一个多晶SiGe栅电极.分析了该结构的电学特性与器件的几何结构参数和材料物理参数的关系,而且还给出了这种器件结构作为反相器的一个应用,模拟了其传输特性.结果表明所设计的垂直层叠共栅结构应变Si/SiGe HCMOS结构合理、器件性能提高.     

Effect of plasma process-induced damage on bias temperature instability of MOSFETs

For a surface-channel n-MOSFET and a buried-channel p-MOSFET, the effect of plasma process-induced damage on bias temperature instability (BTI) was investigated. The gate oxide thickness, t_ox, of the test MOSFETs was 2.0, 3.0, or 4.5 nm. The shifts of threshold voltage V_th and of linear drain current I_dlin were measured after applying a BTI stress at a temperature of 125 °C. The measured shifts of V_th and I_dlin indicate that BTI on ultra-thin gate CMOS devices appears only in the form of SiO₂/Si interface degradation, and that the positive BTI for the n-MOSFET as well as the negative BTI for the p-MOSFET is important for the reliability evaluation of CMOS devices. Because of positive plasma charging to the gate, a protection diode was very efficient at reducing BTI for the p-MOSFET, but it was much less effective for the n-MOSFET.     

应变Si沟道异质结NMOS晶体管

通过参数调整和工艺简化,制备了应变Si沟道的SiGe NMOS晶体管.该器件利用弛豫SiGe缓冲层上的应变Si层作为导电沟道,相比于体Si器件在1V栅压下电子迁移率最大可提高48.5%.     

A dual-strained CMOS structure through simultaneous formation of relaxed and compressive strained-SiGe-on-insulator

This letter reports on an integration of dual-strained surface-channel CMOS structure, i.e., tensile-strained Si n-MOSFET and compressive strained-SiGe p-MOSFET. This has been accomplished by forming the relaxed and compressive strained-SiGe layers simultaneously on an Si/SiGe-on-insulator (SOI) substrate, through varying SiGe film thicknesses, followed by a thermal condensation technique to convert the Si body into SiGe with different [Ge] concentration and with different strains (including the relaxed state). A thin Si film was selectively deposited over the relaxed SiGe region. The p-MOSFET in compressive (/spl epsiv//spl sim/ -1.07%) strained- Si/sub 0.55/Ge/sub 0.45/ and the n-MOSFET in tensile-strained Si over the relaxed Si/sub 0.80/Ge/sub 0.20/ exhibited significant hole (enhancement factor /spl sim/ 1.9) and electron (enhancement factor /spl sim/ 1.6) mobility enhancements over the Si reference.     

Electric-field-shielding layers formed by oxygen implantation into silicon

The electric-field-shielding effect was found in a layer consisting of a mixture of polycrystalline silicon and silicon oxide formed by oxygen ion implanatation. The layer was formed between the buried SiO2 and the upper Si layer, which improved characteristics for MOSFETs fabricated using SIMOX (separation by implanted oxygen) technology. By forming this layer, the threshold voltages for the MOSFETs were almost independent of substrate bias. Drain-to-source breakdown voltages for the p-MOSFETs and n-MOSFETs were raised to 250 V and 180 V, respectively.     

A new asymmetrical halo source GOLD drain (HS-GOLD) deepsub-half-micrometer n-MOSFET design for reliability and performance

An asymmetrical n-MOSFET device structure was developed that is suitable, in terms of reliability and performance, for scaling down to the sub-quarter-micrometer level without reduction of the supply voltage below 3.5 V. In this structure, large-tilt implantation is used to form the gate-overlapped LDD (GOLD) region at the drain electrode only. A halo (punchthrough stopper) is used at the source, but not at the drain. Superior hot carrier reliability and high punchthrough resistance are obtained using this device structure. A reliability-limited supply voltage of 4.2 V is obtained for an asymmetrical n-MOSFET with effective channel lengths as short as 0.25 μm. By extrapolation from the measured threshold roll-off characteristics, the authors expect that this structure can be designed with substantially shorter channel length while maintaining the 3.5-V supply voltage     

Scaling and strain dependence of nanoscale strained-Si p-MOSFET performance

Self-consistent fullband Monte Carlo simulations based on nonlocal empirical pseudopotential band structures including spin-orbit splitting are employed to estimate the on-current in nanoscale strained-Si p-MOSFETs. Effective gate lengths from L/sub eff/ = 75 nm down to L/sub eff/ = 25 nm and strain levels corresponding to germanium contents of up to x = 0.4 in the relaxed Si/sub 1-x/Ge/sub x/ substrate are considered. It is found that the on-current continuously increases for growing substrate germanium contents. The strain-induced performance enhancement moderately decreases with scaling, but the improvement at L/sub eff/ = 25 nm still attains 20% for x = 0.4. In contrast to strained-Si n-MOSFETs, increasing the substrate germanium content beyond x = 0.2 is essential for p-MOSFET performance improvement by strain in the sub 0.1 /spl mu/m regime. However, even for x = 0.4 the on-current in a strained-Si p-MOSFET is still smaller than in a corresponding unstrained-Si n-MOSFET.     

A stacked CMOS technology on SOI substrate

A stacked CMOS technology fabricated on semiconductor-on-insulator (SOI) wafers with the p-MOSFET on the SOI film and the n-MOSFET on the bulk substrate is demonstrated. The technology provides a number of advantages, including: 1) single crystal multi-layer of active devices; 2) self-aligned double-gate p-MOSFET with thick source/drain and thin channel regions; 3) self-aligned channel region of n-MOSFET to p-MOSFET stacked perfectly on top of each other; 4) significant area saving; and 5) reduced interconnect distance and loading. Experimental results show that the fabricated double-gate p-MOSFET has a nearly ideal subthreshold swing and almost the same current drive as the n-MOSFET with the same lateral width, resulting in a highly compact and completely overlap stacked CMOS inverter.