TLP应力下深亚微米GGNMOSFET特性的仿真

对TLP(传输线脉冲)应力下深亚微米GGNMOS器件的特性和失效机理进行了仿真研究.分析表明,在TLP应力下,栅串接电阻减小了保护结构漏端的峰值电压;栅漏交迭区电容的存在使得脉冲上升沿加强了栅漏交叠区的电场,栅氧化层电场随着TLP应力的上升沿减小而不断增大,这会导致栅氧化层的提前击穿.仿真显示,栅漏交迭区的电容和栅串接电阻对GGNMOS保护器件的开启特性和ESD耐压的影响是巨大的.该工作为以后的TLP测试和标准化提供了依据和参考.     

TLP应力下深亚微米GGNMOSFET特性的仿真

对TLP(传输线脉冲)应力下深亚微米GGNMOS器件的特性和失效机理进行了仿真研究. 分析表明，在TLP应力下，栅串接电阻减小了保护结构漏端的峰值电压；栅漏交迭区电容的存在使得脉冲上升沿加强了栅漏交叠区的电场，栅氧化层电场随着TLP应力的上升沿减小而不断增大，这会导致栅氧化层的提前击穿. 仿真显示，栅漏交迭区的电容和栅串接电阻对GGNMOS保护器件的开启特性和ESD耐压的影响是巨大的. 该工作为以后的TLP测试和标准化提供了依据和参考.     

ESD应力下深亚微米GGNMOS二次击穿物理级建模仿真

基于静电放电(ESD)应力下深亚微米栅接地N型场效应晶体管(GGNMOS)二次击穿的物理特性,将建立的热击穿温度模型、热源模型与温度相关参数模型相结合,提出了一种新的电热模型,并进行了优化。基于这些模型,可仿真出器件的二次击穿电流值It2(GGNMOS的失效阈值),进而模拟出GGNMOS全工作区域的VD-ID曲线。对两种不同的GGNMOS样品进行模拟仿真,将得到的结果与TLP(传输线脉冲)实验测试的结果相比较,证实了模型的可行性。利用该物理级模型,可快速评估GGNMOS的工艺、版图参数以及脉冲应力宽度对ESD鲁棒性的影响。     

ESD保护器件GGNMOS二次击穿前的建模

基于ESD应力下GGNMOS的工作特性,从GGNMOS的内部物理过程,推导建立了二次击穿前GGNMOS的器件级模型,并给出了相应的参数提取方法;实现了输入工艺参数等到模型中,即可仿真GGNMOS二次击穿前的I-V特性.通过与TLP实际测试结果的比较,证实了所推导模型的可行性.     

深亚微米ESD保护器件GGNMOS性能分析与设计

本文采用MEDICI作为集成电路ESD保护常用器件—栅极接地NMOS管(GGNMOS)ESD性能分析的仿真工具,综合分析了各种对GGNMOS的ESD性能有影响的因素,如衬底掺杂、栅长、接触孔距离等,为深亚微米下ESD保护器件GGNMOS的设计提供了依据。通过分析发现衬底接触孔到栅极距离对GGNMOS器件ESD性能也有一定影响,此前,对这一因素的讨论较少。最后,根据分析结果,给出了一个符合ESD性能要求的器件设计。     

超薄SiO2软击穿后I-V特性的饱和性质

利用电子速度饱和概念和比例差值方法（proportional difference operator, PDO）研究了超薄SiO2在第一次软击穿以后栅电流随着栅电压的变化所呈现的饱和性质. 实验证明了第一次软击穿以后栅电流随着栅电压变化的PDO谱峰位、峰高与电子在第一次软击穿通道中运动的饱和速度及饱和电流密度相关. 基于缺陷散射机制，得到的第一次软击穿通道的横截面积与文献报导的结果一致.     

超薄SiO2软击穿后I-V特性的饱和性质

利用电子速度饱和概念和比例差值方法(proportional difference operator,PDO)研究了超薄SiO2在第一次软击穿以后栅电流随着栅电压的变化所呈现的饱和性质.实验证明了第一次软击穿以后栅电流随着栅电压变化的PDO谱峰位、峰高与电子在第一次软击穿通道中运动的饱和速度及饱和电流密度相关.基于缺陷散射机制,得到的第一次软击穿通道的横截面积与文献报导的结果一致.     

超薄SiO2软击穿后I-V特性的饱和性质

利用电子速度饱和概念和比例差值方法(proportional difference operator,PDO)研究了超薄SiO2在第一次软击穿以后栅电流随着栅电压的变化所呈现的饱和性质.实验证明了第一次软击穿以后栅电流随着栅电压变化的PDO谱峰位、峰高与电子在第一次软击穿通道中运动的饱和速度及饱和电流密度相关.基于缺陷散射机制,得到的第一次软击穿通道的横截面积与文献报导的结果一致.     

平面型埋栅结构的静电感应晶体管

在表面栅和埋栅结构的基础上,提出了一种制造静电感应晶体管的新型结构,平面型埋栅结构.用普通的平面工艺实现了具有高击穿电压的埋栅结构,避免了工艺难度较大的二次外延和台面腐蚀工艺.实验结果表明该结构可用于制造各种功率静电感应器件,其优点是具有高的击穿电压和高的阻断增益,并讨论了平面型埋栅结构的主要特点和制造工艺.     

平面型埋栅结构的静电感应晶体管

在表面栅和埋栅结构的基础上,提出了一种制造静电感应晶体管的新型结构,平面型埋栅结构.用普通的平面工艺实现了具有高击穿电压的埋栅结构,避免了工艺难度较大的二次外延和台面腐蚀工艺.实验结果表明该结构可用于制造各种功率静电感应器件,其优点是具有高的击穿电压和高的阻断增益,并讨论了平面型埋栅结构的主要特点和制造工艺.     

用于200V电平位移电路的薄层SOI高压LDMOS

文章基于1.5μm厚顶层硅SOI材料,设计了用于200 V电平位移电路的高压LDMOS,包括薄栅氧nLDMOS和厚栅氧pLDMOS。薄栅氧nLDMOS和厚栅氧pLDMOS都采用多阶场板以提高器件耐压,厚栅氧pLDMOS采用场注技术形成源端补充注入,避免了器件发生背栅穿通。文中分析了漂移区长度、注入剂量和场板对器件耐压的影响。实验表明,薄栅氧nLDMOS和厚栅氧pLDMOS耐压分别达到344 V和340 V。采用文中设计的高压器件,成功研制出200 V高压电平位移电路。     

Off-state breakdown in power pHEMTs: the impact of the source

Conventional wisdom suggests that in pseudomorphic high electron mobility transistors (pHEMTs), the field between the drain and the gate determines off-state breakdown, and that the drain to gate voltage therefore sets the breakdown voltage of the device. Thus, the two terminal breakdown voltage is a widely used figure of merit, and most models for breakdown focus on the depletion region in the gate-drain gap, while altogether ignoring the source. We present extensive new measurements and simulations that demonstrate that for power pHEMTs, the electrostatic interaction of the source seriously degrades the device's gate-drain breakdown. We identify the key aspect ratio that controls the effect, L_G:x_D where L_G is the gate length and x_D is the depletion region length on the drain. This work establishes that the design of the source must be taken into consideration in the engineering of high-power pHEMT's     

Microwave power double-heterojunction HEMT's

The RF and dc characteristics of microwave power double-heterojunction HEMt's (DH-HEMT's) with low doping density have been studied. Small-signal RF measurements indicated that the cutoff frequency and the maximum frequency of oscillation in DH-HEMT's with 0.8-1 µm gate length and 1.2 mm gate periphery are typically 11- 16 GHz and 36-41 GHz, respectively. However, the cutoff frequency in DH-HEMT's degrades strongly with increasing drain bias voltage. This may be caused by both effects of increasing effective transit length of electrons and decreasing average electron velocity, due to Gunn domain formation. In large-signal microwave measurement, the DH-HEMT (2.4 mm gate periphery) delivered a maximum output power of 1.05 W with 2.8 dB gain and 0.58 W with 1.6 dB gain at 20 and 30 GHz, respectively. These are the highest output powers yet reported for HEMT devices. For the dc characteristics, the onset of two-terminal gate breakdown voltage is found to correlate with the drain current Idssand recessed length, and three-terminal source-drain breakdown characteristics near pinchoff are limited by the gate-drain breakdown. A simple model on gate breakdown voltage in HEMT is also presented.     

A new shallow trench and planar gate MOSFET structure based on VDMOS technology

This paper proposes a new shallow trench and planar gate MOSFET(TPMOS) structure based on VDMOS technology,in which the shallow trench is located at the center of the n~- drift region between the cells under a planar polysilicon gate.Compared with the conventional VDMOS,the proposed TPMOS device not only improves obviously the trade-off relation between on-resistance and breakdown voltage,and reduces the dependence of on-resistance and breakdown voltage on gate length,but also the manufacture process is compatible with that of the VDMOS without a shallow trench,thus the proposed TPMOS can offer more freedom in device design and fabrication.     

RF LDMOS功率器件研制

基于ISE TCAD模拟软件对RF LDMOS器件的工艺流程和器件结构进行了优化设计,采用带栅极金属总线的版图结构降低栅电阻,同时简化了LDMOS器件的封装设计.通过实际流片和测试分析,重点讨论了漂移区注入剂量和漂移区长度对LDMOS器件的转移特性、击穿特性、截止频率及最大振荡频率的影响.测试结果表明该器件的阈值电压为1.8 V,击穿电压可达70 V,截止频率和最大振荡频率分别为9 GHz和12.6 GHz,并可提供0.7 W/mm的输出功率密度.     

High-voltage TFT fabricated in recrystallized polycrystallinesilicon

High-voltage thin-film transistors (TFTs) fabricated using CW-Ar laser annealed polycrystalline silicon have an offset gate structure between the source and gate and between the gate and drain. The breakdown voltage, transconductance, and leakage current in various size TFTs are described. These TFTs exhibited n-channel enhancement characteristics with a low-threshold voltage, and a breakdown voltage above 100 V could be obtained at an offset gate length of 20 μm. Active TFT circuits were fabricated with these high-voltage Si TFTs. These high-voltage TFT circuits can drive thin-film EL (electroluminescent display) at low signal voltage     

MOSFET栅下碰撞电离与击穿研究

研究了场板终端技术对改善 MOSFET栅下电场分布和碰撞电离率的作用 ,结果表明 ,MOSFET在高压应用时 ,漏极靠近表面的 PN结处电场最强 ,决定器件的击穿特性。通过对实验研究与计算机模拟结果的分析 ,表明在不同的栅压下 ,此处场板长度的大小对栅下电场强度有直接的影响 ,合理地控制场板长度能有效地提高器件的击穿电压。     

Diamond surface-channel FET structure with 200 V breakdown voltage

An enhancement mode diamond FET using a hydrogen-terminated surface as hole conductive channel has been fabricated with 200 V gate to drain breakdown voltage. At the 8.5-μm gate length the maximum drain current was 22 mA/mm. 90 mA/mm maximum drain current was obtained at a gate length of 3.0 μm. Scaling to below 1 μm gate length assuming undegraded breakdown conditions will result in a projected RF power handling capability above 6 W/mm     

具有L型栅极场板的双槽双栅绝缘体上硅器件新结构

为了降低绝缘体上硅（SOI）功率器件的比导通电阻,同时提高击穿电压,利用场板（FP）技术,提出了一种具有L型栅极场板的双槽双栅SOI器件新结构.在双槽结构的基础上,在氧化槽中形成第二栅极,并延伸形成L型栅极场板.漂移区引入的氧化槽折叠了漂移区长度,提高了击穿电压;对称的双栅结构形成双导电沟道,加宽了电流纵向传输面积,使比导通电阻显著降低;L型场板对漂移区电场进行重塑,使漂移区浓度大幅度增加,比导通电阻进一步降低.仿真结果表明：在保证最高优值条件下,相比传统SOI结构,器件尺寸相同时,新结构的击穿电压提高了123%,比导通电阻降低了32%;击穿电压相同时,新结构的比导通电阻降低了87.5%;相比双槽SOI结构,器件尺寸相同时,新结构不仅保持了双槽结构的高压特性,而且比导通电阻降低了46%.     

新型双RESURF TG-LDMOS器件结构

研究了采用双RESURF技术的槽栅横向双扩散MOSFET（DRTG-LDMOS），讨论了双RESURF技术对击穿电压的影响，以及DRTG-LDMOS的电容特性，与传统的槽栅器件结构相比，新结构在相同的漂移长度和导通电阻下，击穿电压提高了30V，并表现出优异的频率特性；