DSP implementations of sophisticated speech codecs

Hardware implementation aspects of sophisticated speech codecs are addressed. The major points discussed are approaches to implementation of the sophisticated speech codecs, requirements for DSP (digital signal-processing) implementation of the codecs, such as the type of arithmetic processing and the necessity of bit-level specifications, and codec implementation and DSP programming techniques for three specific coding algorithms: 32-kb/s ADPCM (adaptive digital pulse code modulation), 64-kb/s (7 kHz) SB (subband)-ADPCM, and 16-kb/s APC-AB (adaptive predictive coding with adaptive but allocation) codecs     

High-voltage TFT fabricated in recrystallized polycrystallinesilicon

High-voltage thin-film transistors (TFTs) fabricated using CW-Ar laser annealed polycrystalline silicon have an offset gate structure between the source and gate and between the gate and drain. The breakdown voltage, transconductance, and leakage current in various size TFTs are described. These TFTs exhibited n-channel enhancement characteristics with a low-threshold voltage, and a breakdown voltage above 100 V could be obtained at an offset gate length of 20 μm. Active TFT circuits were fabricated with these high-voltage Si TFTs. These high-voltage TFT circuits can drive thin-film EL (electroluminescent display) at low signal voltage     

Echo cancellation and applications

Practical echo cancellation techniques, in particular, those used in telecommunications, are reviewed. The various situations in which echoes are generated are examined. Echo path modeling techniques and adaptive algorithms for coefficient control are reviewed. Current international standardization activities are discussed, and echo canceler implementation considerations are set forth. These include echo cancelers for telephone circuits, echo cancelers for full-duplex data transmission over voice channels, acoustic echo cancelers, and echo cancelers for ISDN digital loop transmission     

Novel phenomenon of avalanche breakdown saturation with negativeresistance in a bipolar transistor

A breakdown saturation phenomenon of negative resistance has been observed in a bipolar transistor. The collector current becomes saturated and reaches a critical current (I_CC) after avalanche breakdown. At this critical current, a negative resistance appears. I_CC is determined by the thermal condition of the transistor, as obtained from pulse measurements and temperature dependence. For the multiplication factor (M), it is clear that there are two distinct regions: 1) low voltage (Region I) and 2) higher voltage (Region II). In Region I, the multiplication factor begins to increase with increasing applied voltage and is fixed almost constant for temperature, whereas in Region II, the multiplication factor decreases with increasing temperature. As a result, (∂M/∂V) _T≃0 is realized at about 20 V and 124°C, corresponding to the saturation of avalanche breakdown     

LSI Processor for Digital Signal Processing and Its Application to 4800 Bit/s Modem

This paper describes a fast data processing LSI unit tailored to the digital signal processing (DSP) applications in the field of electrical communications. The results of successful application to the 4800 bit/s modem are also given. The LSI processor discussed here adopts a firmware control scheme to enhance the flexibility and freedom of application and extensively utilizes the pipeline processing technique to attain high speed data handling capability. The various operations encountered in DSP systems are unified into one operation of the typeA times B + C rightarrow Dand the LSI processor is designed to continuously perform this operation, while the data to be operated are transferred sequentially into the processor controlled by exterior firmware. The developed LSI handles 8 bit data at the clock frequency of 1.152 MHz and manages 144 K operations per second (6.9 μs cycle time). The LSI is an N-MOS chip containing 1500 gates and packaged in a 40 pin DIP. The automatic equalizer for 4800 bit/s modem was implemented using two of the developed LSI processors and about 4 K ROM and 1 K RAM memory chips. The measurement on this modem gave the error rate of 10^-5atS/N = 17.6dB and error free phase jitter allowance of 55° p-p. Application of the LSI processor to digital filters for roll-off spectrum shaping and timing signal extraction is also described.     

EL characteristics of a TFEL/TFT stacked structure display devicedriven by a HV-Si·TFT circuit

TFEL/TFT stacked structure display devices were fabricated onto a quartz substrate. By using a HV-TFT circuit as the basis of a TFEL/TFT device, an EL device on the TFT circuit can be switched at a sufficiently low signal line voltage of V_s=2-3 V. The maximum brightness of the TFEL/TFT device is 230 cd/m² and the ON/OFF brightness ratio is more than 90 between Vs=0 and Vs=4 V at a V_app frequency of 5 kHz and a voltage of 50. Evaluation of the dynamic behavior of TFT circuits using multichannel HV-Si·TFT's showed that the rise time of the fundamental TFT circuit at the EL driving point of the circuit was about 20 μs and that the hold time of the circuit was about 70 mS. The rise time and the fall time of the luminescence were each about 20 μs. The memory characteristics of the TFEL/TFT device showed that the hold time of the luminescence was about 40 mS. These dynamic characteristics of the TFEL/TFT stacked structure device satisfy the conditions required for a flat panel display     

ADPCM with a multiquantizer for speech coding

A speech coding algorithm with low complexity and a short processing delay is introduced. The proposed algorithm is ADPCM (adaptive digital pulse code modulation) with a multiquantizer (ADPCM-MQ). The input signal is processed in parallel by multiple ADPCM coders with different characteristics. Then the optimum ADPCM coder with minimum error power is dynamically selected for each frame. A 16-kb/s codec based on this algorithm has been implemented using two general-purpose digital signal processors (MB8764) with 8.3 ms of total processing delay. A segmental SNR of 19-21 dB was achieved at 16 kb/s; with postfiltering the segmental SNR was increased to 23-25 dB. Combined with the time domain compression scheme, the algorithm can be easily applied to 8-kb/s coding. It is also extensible to variable-rate coding     

High-performance poly-Si TFTs with ECR-plasma hydrogen passivation

High-performance thin-film transistors (TFTs) with electron-cyclotron resonance (ECR) plasma hydrogen passivation fabricated by the use of laser-recrystallized multiple-strip-structure poly-Si film are discussed. These TFTs have n-channel enhancement-mode characteristics with a large transconductance, a high switching ratio, and a threshold voltage as low as 0.4 v. The ECR-plasma hydrogen passivation of laser-recrystallized poly-Si, reduces the trap density of poly-Si and increases the carrier mobility thus, desirable TFT characteristics are obtained. This passivation increased the transconductance (g_m) of a TFT and decreased the leakage current between the source and the drain. As a result, a switching ratio as high as 2.5×10⁹ and very low leakage current of the order of 10¹⁴ A can be achieved by these high-performance TFTs