一种带新型直流失调补偿电路的模拟数字控制可配置的自动增益控制器

本文提出一种可用于零中频接收机的模拟/数字控制可配置的自动增益控制环路的设计,应用一种新型的直流失调消除电路。这种自动增益控制环路可配置于模拟或者数字控制,以便与不同的基带芯片兼容。本文更进一步提出了一种新型的直流失调消除电路,这种直流失调消除电路实现了低于10KHz的下限截止频率（HPCF,high pass cutoff frequency）。自动增益控制环路电路采用0.18um CMOS工艺。当配置于模拟控制模式下,这种自动增益控制环路的增益动态范围为70dB,3dB带宽大于60M。当配置于数字控制模式下,通过5比特的数字控制码控制,这种自动增益控制环路的增益动态范围为64dB,步进精度2dB,步进误差小于0.3dB。当输入引入40mV直流失调,电路输出直流失调电压小于1.5mV。电路整体功耗小于3.5mA,面积800um*300um。     

带有DCOC结构的中频可编程增益放大器

介绍了一种用于射频识别接收机、能有效消除直流失调的中频可编程增益放大器.单级放大器的仿真结果可提供.10～20 dB的增益控制范围,增益步长为2 dB,增益误差小于0.3 dB.通过在直流失调消除环路中增加一级滤波器的方法,有效地降低了直流失调和低频噪声,在40 kHz工作频率下等效输入噪声电压38.04 nV/ Hz,直流失调消除电路可将输出直流失调量抑制在输入失调量的2%范围以内.电路采用0.18μm IP6M CMOS工艺实现.     

用于UHF RFID阅读器的自动频率校准模拟基带

基于0.18μm标准CMOS工艺,提出了一种适用于超高频射频识别阅读器的自动频率校准模拟接收基带。该模拟基带包含直流偏移消除电路和信道选择滤波器,直流偏移消除电路有6dB的预增益,信道选择滤波器采用8阶巴特沃斯结构。在频率校准电路的作用下,滤波器能够分别对250kHz和1.35MHz截止频率进行校准,校准时间小于3μs。后仿真结果表明,在3.3V电源电压下,整个模拟基带消耗12mA电流,截止频率为1.35MHz,10dB增益条件下带内输入3阶交调达到12dBm,在30dB增益时,带内噪声系数为26dB。     

一种应用于IEEE 802.11 b/g/n无线局域网收发机的CMOS模拟基带电路

本文提出了一种应用于直接变频无线局域网收发机的模拟基带电路,该电路采用标准的0.13微米CMOS工艺实现,包括了采用有源RC方式实现的接收4阶椭圆低通滤波器、发射3阶切比雪夫低通滤波器、包含直流失调消除伺服环路的接收可变增益放大器及片上输出缓冲器。芯片面积共1.26平方毫米。接收基带链路增益可在-11dB至49dB间以2dB步长调节。相应地,基带接收输入等效噪声电压（IRN）在50 nV/sqrt(Hz) 至30.2 nV/ sqrt(Hz)间变化而带内输入三阶交调（IIP3）在21dBm至-41dBm间变化。接收及发射低通滤波器的转折频率可在5MHz、10MHz及20MHz之间选择以符合包含802.11b/g/n的多种标准的要求。接收基带I、Q两路的增益可在-1.6dB至0.9dB之间以0.1dB的步长分别调节以实现发射IQ增益失调校正。通过采用基于相同积分器的椭圆滤波器综合技术及作用于电容阵列的全局补偿技术,接收滤波器的功耗显著降低。工作于1.2V电源电压时,整个芯片的基带接收及发射链路分别消耗26.8mA及8mA电流。     

一种低失调高压大电流集成运算放大器

基于结型场效应晶体管(JFET)和双极型晶体管(BJT)兼容工艺,设计了一种低失调高压大电流集成运算放大器。电路输入级采用p沟道JFET (p-JFET)差分对共源共栅结构;中间级以BJT作为放大管,采用复合有源负载结构;输出级采用复合npn达林顿管阵列,与常规推挽输出结构相比,在输出相同电流的情况下,节省了大量芯片面积。基于Cadence Spectre软件对该运算放大器电路进行了仿真分析和优化设计,在±35 V电源供电下,最小负载电阻为6Ω时的电压增益为95 dB,输入失调电压为0.224 5 mV,输入偏置电流为31.34 pA,输入失调电流为3.3 pA,单位增益带宽为9.6 MHz,具有输出9 A峰值大电流能力。     

一种新颖的可应用于多模多频接收机可配置的可变增益放大器

本文阐述了一种新颖的可应用于多模多频接收机射频前端可配置的可变增益放大器的设计方法。可变增益放大器包括增益放大电路,控制电路,直流失调消除电路和模式转换电路四个部分。这种结构可以在保证多模多频应用的前提下通过硬件复用最大化来节省芯片面积和功耗。电路采用0.18 um CMOS 工艺,在1.8V的供电电压下可实现5dB 至87dB的动态范围,电路的带宽（所有增益下）大于80 MHz。此外,直流失调消除电路有效抑制了直流失调成分至小于40mV。整个电路的功耗小于3mA,面积为705um*100um。     

一种用于生物信号采集的CMOS全差分前置跨阻放大器设计

针对生物信号微弱、变化范围大等特点设计了一种用于检测微弱电流的全差分跨阻放大器(TIA)电路结构。不同于传统电路的单端输入,该结构采用高增益的全差分两级放大器实现小信号输入及轨到轨输出。基于CSMC 0.18μm CMOS工艺,采用1.8V电源电压对设计的电路进行了仿真,仿真结果表明:TIA输入电流动态范围为100nA^10μA,最大跨阻增益达到104.38dBΩ,-3dB带宽为4MHz,等效输入噪声电流为1.26pA/Hz。对电路进行跨阻动态特性仿真表明,在输入电流为100nA时,输出电压的动态摆幅达到3.24mV,功耗仅为250μW,总谐波失真(THD)为-49.93dB。所设计的高增益、低功耗、宽输入动态范围TIA适用于生物医疗中极微小生物信号的采集,可作为模块电路集成在便携设备中。     

一种可应用于零中频接收机的自动增益控制环路设计

阐述了一种可用于零中频接收机的自动增益控制环路(AGE)的设计,应用一种并行补偿的直流失调消除电路,可有效抑制前级模块引入及电路本身失配导致的直流失调成分.相比传统的反馈式直流失调消除电路,该并行补偿电路具有抑制效果更好,更易实现较低下截止频率HPCF(Hish Pass Cutoff Frequency)的特点,同时不存在反馈式结构的稳定性问题.电路采用0.18 μm CMOS工艺,1.8 V供电电源,可稳定输出700 mVp-p电压,增益动态范围为50 dB,3 dB带宽大于60 M,下截止频率低于10 kHz.电路输出直流失调电压小于5 mV,功耗4.31 mA,面积710 μm×110 μm.     

低功耗、高线性度的电流模可编程增益放大器

本文设计了一种电流模式下,带电流模直流失调消除（DCOC）电路的class-AB的可编程增益放大器。电路基于电流放大器,可以实现40dB的增益动态范围,增益步长为1dB。电流模可编程增益放大器由0.18-μm CMOS工艺实现,电路具有较宽的电流增益范围、较低的直流功耗和较小的芯片面积。放大器电路芯片面积为0.099μm2,在1.8V电压下静态电流为2.52mA。测试结果表明电路增益范围为10dB到50dB,增益误差为±0.40dB,OP1dB为11.80dBm到13.71dBm,3dB带宽为22.2MHz到34.7MHz。     

一种用于传感器模拟前端的可编程增益放大器

基于华虹0.18μm CMOS工艺设计了一款用于传感器模拟前端的可编程增益放大器(PGA),其整体采用全差分结构来抑制传感器输出的共模噪声、直流分量以及供电电源的输出噪声。该电路由仪表放大结构轨对轨输入级、轨对轨自动调零全差分运算放大器、数字控制电路以及直流分量消除电路这四个部分构成,同时采用连续时间自动调零校准技术来降低其输入失调电压。PGA的放大倍数为5 bit调节,共12个档位,分别为1,2,4,8,…,1024,2048倍。在3.3 V电源电压下,PGA输入输出摆幅为0.2～3.1 V。在输入500 mV的直流分量条件下,在-40～125℃的温度范围内,可将直流分量抑制到47.6μV。通过Virtuoso软件进行电路设计、版图绘制以及仿真验证,后仿真结果表明,在进行100次蒙特卡罗仿真下,电源抑制比和共模抑制比在1 kHz处的平均值分别约为110.3 dB和116.1 dB,输入失调电压的1σ值约为21.3μV。     

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control(AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented.The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips.What’s more,a novel DC offset cancellation(DCOC) circuit with an HPCF(high pass cutoff frequency) less than 10 kHz is proposed.The AGC is fabricated by a 0.18μm CMOS process.Under analog control mode,the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz.Under digital control mode,through a 5-bit digital control word,the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB.The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV,while the offset voltage of 40 mV is introduced into the input.The overall power consumption is less than 3.5 mA,and the die area is 800×300μm~2.     

A MOS switched-capacitor instrumentation amplifier

Describes a precision switched-capacitor sampled-data instrumentation amplifier using NMOS polysilicon gate technology. It is intended for use as a sample-and-hold amplifier for low level signals in data acquisition systems. The use of double correlated sampling technique achieves high power supply rejection, low DC offset, and low 1/f noise voltage. Matched circuit components in a differential configuration minimize errors from switch channel charge injection. Very high common mode rejection (120 dB) is obtained by a new sampling technique which prevents the common mode signal from entering the amplifier. This amplifier achieves 1 mV typical input offset voltage, greater than 95 dB PSRR, 0.15 percent gain accuracy, 0.01 percent gain linearity, and an RMS input referred noise voltage of 30 /spl mu/V/input sample.     

一种用于水听器电压检测的模拟前端电路

提出了一种用于水听器电压检测的模拟前端电路,包括低噪声低失调斩波运算放大器,跨导电容(gm-C)低通滤波器,增益放大器三部分主体电路;低噪声低失调斩波运算放大器用于提取水听器前端传感器输出的微弱电压信号;gm-C低通滤波器用于滤除电压信号频率外的高频噪声和高次谐波;最后经过增益放大器放大至后级模数转换器的输入电压范围,输出数字码流;芯片采用台积电(TSMC)0.18μm单层多晶硅六层金属(1P6M)CMOS工艺实现。测试结果表明,在电源电压1.8 V,输入信号25 kHz和200 kHz时钟频率下,斩波运放输入等效失调电压小于110μV;整体电路输出信号动态范围达到80 dB,功耗5.1 mW,满足水听器的检测要求。     

程控增益低噪声宽带直流放大器的设计

介绍了程控增益低噪声宽带直流放大器的设计原理及流程。采用低噪声增益可程控集成运算放大器AD603和高频三极管2N2219和2N2905等器件设计了程控增益低噪声宽带直流放大器,实现了输入电压有效值小于10mV,输出信号有效值最大可达10V,通频带为0～8MHz,增益可在0～50dB之间5dB的步进进行控制,最高增益达到53dB,且宽带内增益起伏远小于1dB的两级宽带直流低噪声放大器的设计。     

SOI温度补偿效应的全集成高线性度Gm-C滤波器设计

提出了一种全差分运算放大器,该运算放大器采用电压负反馈方式稳定输出共模电平, 调节输入差分管相应的衬底偏置改变输入对的阈值电压差,从而调节放大器的跨导来调整滤波器的截止频率,这样可以补偿温度变化对滤波器频响造成的漂移。实现了基于Gm-c结构的三阶Chebyshev低通滤波器,该滤波器采用GSMC的0.13um SOI工艺,电源电压1.2v,6层金属设计,仿真结果表明,该滤波器通带增益0dB,-1dB截止频率8MHZ,38MHZ处增益衰减达到-35dB,带内波动0.5dB,输入为1MHZ,400mVpp时,THD为-57dB,,功耗7mW.     

A programmable gain amplifier with a DC offset calibration loop for a directconversion WLAN transceiver

A high-linearity PGA(programmable gain amplifier) with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA(RXPGA) provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA(TXPGA) covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA (I and Q path) under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC(DC offset cancellation) circuit shows 10 kHz of HPCF(high pass cutoff frequency) and the DCOC settling time is less than 0.45μs.     

A low-noise CMOS instrumentation amplifier for thermoelectricinfrared detectors

A low-noise CMOS instrumentation amplifier for low-frequency thermoelectric infrared sensor applications is described which uses a chopper technique to reduce low-frequency noise and offset. The offset reduction efficiency of the band-pass filter, implemented to reduce residual offset due to clock feedthrough, has been analyzed and experimentally verified. The circuit has been integrated in a transistor-only 1-μm single-poly n-well CMOS process. It features a gain of 52 dB with a 500 Hz bandwidth and a common-mode rejection ratio (CMRR) of more than 70 dB. The equivalent input low frequency noise is 15 nV/√Hz. The typical residual input offset is 1.5 μV. The amplifier power consumption is 1.3 mW     

应用于802.11b无线局域网的低噪声高线性度的CMOS射频接收机

实现了一个单片集成、直接转换结构的2.4GHz CMOS接收机.这个正交接收机作为低成本方案应用于802.11b无线局域网系统,所处理的数据传输率为该系统的最大速率--11Mbps.基于系统设计以及低噪声高线性度考虑,设计了低噪声放大器、直接转换混频器、增益可变放大器、低通滤波器、直流失调抵消电路及其他辅助电路.该芯片采用中芯国际0.18μm 1p6m RF CMOS工艺流片.所测的接收机性能如下:噪声系数为4.1dB,高增益设置下低噪声放大器与混频器的输入三阶交调点为-7.5dBm,整个接收机的输入三阶交调点为-14dBm,相邻信道干扰抑制能力在距中心频率30MHz处达到53dBc,输出直流失调电压小于5mV.该接收机采用1.8V电源电压,I,Q两路消耗的总电流为44mA.     

A 2.5-V 56-mW baseband chain in a multistandard TV tuner for mobile and multimedia applications

This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process.A programmable 7th-order Chebyshev low pass filter with a calibration circuit is used in the analog baseband chain,and the programmable bandwidth is 1.8/2.5/3/3.5/4 MHz with an attenuation of 26/62 dB at offsets of 1.25/4 MHz.The baseband programmable gain amplifier can achieve a linear 40-dB gain range with 0.5-dB steps.Design trade-offs are carefully considered in designing the baseband circuit,and an automatic calibration circuit is used to achieve the bandwidth accuracy of 2%.A DC offset cancellation loop is also introduced to remove the offset from the layout and self-mixing,and the remaining offset voltage is only 1.87 mV.Implemented in a 0.13-μm SiGe technology with a 0.6-mm~2 die size,this baseband achieves IIP3 of 23.16 dBm and dissipates 22.4 mA under a 2.5-V supply.     

A 4th-order reconfigurable analog baseband filter for software-defined radio applications

This paper presents a 4th-order reconfigurable analog baseband filter for software-defined radios.The design exploits an active-RC low pass filter（LPF） structure with digital assistant,which is flexible for tunability of filter characteristics,such as cut-off frequency,selectivity,type,noise,gain and power.A novel reconfigurable operational amplifier is proposed to realize the optimization of noise and scalability of power dissipation.The chip was fabricated in an SMIC 0.13μm CMOS process.The main filter and frequency calibration circuit occupy 1.8×0.8 mm² and 0.48×0.25 mm² areas,respectively.The measurement results indicate that the filter provides Butterworth and Chebyshev responses with a wide frequency tuning range from 280 kHz to 15 MHz and a gain range from 0 to 18 dB.An IIP3 of 29 dBm is achieved under a 1.2 V power supply.The input inferred noise density varies from 41 to 133 nV/（Hz）^1/2 according to a given standard,and the power consumptions are 5.46 mW for low band（from 280 kHz to 3 MHz） and 8.74 mW for high band（from 3 to 15 MHz） mode.