用于UHF RFID的功率放大器设计

功率放大器是UHF RFID系统的重要模块,也是RFID系统中功耗最大的器件。本文采用TSMC0.18rf CMOS工艺,设计了一款用于RFID的线性功率放大器。在915 MHz频段,最大输出功率为17.8 dBm,饱和效率达到了40%,输出1 dB压缩点(P1dB)为15.4 dBm,其小信号增益达到了28.7 dB。     

一种高线性度宽带可编程增益放大器

设计了一种应用于超宽带无线接收机的高线性度宽带可编程增益放大器(PGA),该PGA采用线性度增强型源简并结构的放大器加电阻衰减网络的结构,增益的调节分两步完成,PGA Core实现6dB增益调节步长,电阻衰减网络实现1dB增益调节步长,PGA Core电路采用线性度增强型源简并结构放大器,提高PGA的线性度。PGA采用SMIC 0.18μm混合信号CMOS工艺,1.8 V电源电压供电,仿真结果表明,该PGA增益范围-4~28dB,1dB步进,3dB带宽大于280 MHz,最大增益时输出三阶交调点(OIP3)25.7dBm,噪声系数(NF)22.24dB,总体电路消耗10.4 m A电流,芯片有效面积0.2 mm~2。     

5GHz高线性度CMOS混频器的设计

文中分析了混频器的线性度与转换增益之间的关系,提出了一种提高Gilbert混频器线性度的方法,并设计了5GHz频段适用于802.11a标准的高线性度混频器.电路采用0.18μm CMOS工艺,通过Cadence SpectreRF仿真与优化,得到10.25dBm的1 dB压缩点,-2.24 dB的转换增益,26 dB的噪声系数,整个混频器达到了较高的线性度.     

基于噪声抵消和线性度提高的差分LNA的设计

基于TSMC 0.18μm CMOS工艺,设计了一种低噪声、高增益、高线性度的差分CMOS低噪声放大器。与传统的共源共栅结构相比,在共栅极上引入一对交叉耦合电容和电感,以消除共栅极的噪声并提高电路的线性度和增益。仿真结果表明,在2.45GHz的工作频率下,该电路的噪声系数仅有1.3 dB,该电路能够提供17.8 dB的正向增益,良好的输入输出匹配,该放大器的输入三阶交调点为-0.9 dBm,功耗小于10 mW。     

DC到2.6GHz硅基MMIC放大器

本文采用基于硅基的：BiCMOS工艺设计制作了一款带宽为DC到2．6GHZ的低噪声、高增益MMIC放大器。该放大器为了实现从DC到2．6GHz的带宽，保证有足够的增益和理想的增益平坦度，采用了负反馈结构，两级级联，并选用了一种结构新颖的微波晶体管。该放大器具有功率增益高、频带较宽、噪声系数较小的特点。在仿真过程中其3dB带宽约3GHz，增益为26．6dB(1．5GHz时)，1dB压缩点输出功率约为1dBm；样品的实测结果为3dB带宽约2．6GHz，增益为26dB(1．5GHz时)，1dB压缩点输出功率约为1dBm。     

具有非平衡变换功能的CMOS LNA设计

采用TSMC 0.18μm CMOS工艺设计了一个工作在2.4GHz上,具有非平衡变换功能的低噪声放大器。电路由两级构成,第一级主要实现高增益低噪声,第二级主要实现非平衡变换的功能。仿真结果显示噪声系数小于1dB,增益大于28.5dB,输入三截交调点为-10.27dBm,输出差分信号相位误差小于0.2°,增益差小于0.1。     

Ka频段低杂散上变频器设计及实现

介绍了一种低杂散Ka频段上变频器的设计,对其中的关键电路进行了较为详细的描述,对杂散产生及抑制的关键技术进行了分析。研制的Ka频段上变频器将甚高频(UHF)频段中频信号上变频至Ka频段,1dB压缩点输出功率大于+17dBm,输出中频带宽内增益平坦度小于3dB,杂散抑制优于50dBc。试验测试结果表明,设计为低杂散上变频器提供了一种适宜工程实现的方法。     

带自适应控制的直放站线性功率放大器

线性功率放大器是CDMA直放站的核心模块.本文设计的带自适应控制的线性功放,其功率增益G为48 0.8dB,1db压缩点输出功率≥37dBm,带内渡动≤0.8dB,互调失真IMD3≤-15dBm,IMD5≤-25dBm,输入输出端口驻波比VSWR≤1.3,增益步进衰减ATT范围为31dB,自动电平控制ALC范围为20dB,符合直放站的应用要求.     

低电压高增益下变频混频器设计

本文设计一个低电压高增益下变频混频器。为了降低电源电压,本文采用了LC-tank折叠结构,同时为了提高混频器线性度,采用了开关对共源节点谐振技术。在低电源电压和高线性得到保证的情况下,本文用ADS2009软件重点对混频器的转换增益进行优化、仿真,结果表明:工作电压1.4V,RF频率2.5GHz,本振频率2.25GHz,中频频率250MHz,转换增益7.325dB,三阶交调点6.203dBm,单边带噪声系数3.823dB,双边带噪声系数2.868dB,功耗14.028mW,本文所设计的混频器可用于无线通信领域的电子系统中。     

基于电感源极退化技术的高线性混频器设计

基于电感源极退化技术设计了一款新颖的高线性度正反馈跨导放大器,并且将该跨导放大器应用于折叠结构式混频器当中。通过抵消反相器和辅助放大器之间的三阶跨导分量,改善了其线性度。电路采用TSMC 0.13μm CMOS工艺进行设计与仿真,完成了版图设计与流片。与传统结构相比,该混频器的输入三阶交调点IIP3高达8.6 dBm,噪声系数为10.9 dB,增益高达14 dB,并且取得了更优的归一化FOM指标。     

A novel compact low-power direct conversion receiver for mobile UHF RFID reader

A novel direct conversion receiver with low cost and low power is implemented in a 0.18 μm 1P6M standard CMOS process for a Mobile UHF RFID reader.A highly linear active mixer with low flicker noise and low noise active load is proposed.An efficient and low cost on-chip DC offset voltage canceling scheme is adopted with a high-input-impedance four-input OPAMP to buffer the output of the DC offset canceller(DCOC) block.The receiver has a measured input 1 dB compression point of 2 dBm and a sensitivity of 72 dBm in the presence of the large leakage signal from the transmitter.Only occupying a silicon area of 2.5 mm 2 and consuming 21 mA from a 1.8 V supply,the receiver makes the mobile UHF RFID reader to communicate with a transponder in a distance of 1 m conveniently.     

超高频RFID读写器系统的设计与实现

采用ARM9微处理器为主控制器,射频处理采用奥地利微电子公司的AS3992芯片为核心,设计开发了超高频RFID读写器系统。系统设计了外置功率放大电路、功率探测电路和天线端阻抗匹配调谐电路,使发射机输出功率达到+33dBm,并有效地提高了接收机信噪比,实现了对符合ISO/IEC 18000-6C 900MHz RFID协议的多标签的稳定高速读写;同时在ARM9硬件平台上移植了嵌入式Linux系统,并设计了读写器Web固件控制系统,以实现多标签盘存和读写器的网络配置等操作,为读卡器之间数据通信和二次开发提供平台。该系统已搭建运行于某电厂运煤车辆出入RFID管理控制系统中,运行结果表明,系统最大稳定读取距离达到10m,满足了工程需求。     

A leakage current suppression technique for cascade SRAM array in 55 nm CMOS technology

Sub-threshold leakage is a major issue for low power circuits design, especially for SRAM design in SoC. Sub-threshold leakage can be decreased by scaling down supply voltage. However, this may dramatically increase the circuit delay. In this paper, we propose a novel 6 T SRAM array structure with a switch module which operates in the near threshold region to reduce the leakage current. In order to verify our proposed leakage reduction scheme, we designed and simulated an 8192 kB SRAM array based on a 16 KB single port SRAM cell memory model in 55 nm process. Several 6 T SRAM Array instances are implemented in 55-nm 1P6M CMOS technology to measure the standby current of the proposed scheme as well. With the proposed technique~ we achieved 28.3% reduction for leakage current compared to traditional 6 T SRAM array, in standby mode where gate leakage is dominant. The total penalty is 2% area increase and 1% speed reduction.     

超高频RFID读写器数字接收机设计

针对超高频无源标签返回信号能量差异显著、数据率偏差大的特点,提出一种超高频无线射频识别(RFID)读写器数字接收机的实现方案。采用包含功率估计、数字锁相环同步和差分解码等模块的接收机方案,实现快速准确的接收。该数字接收机经过Matlab仿真验证,在Xilinx Spartan3E平台上实现并测试通过。与常用的多组相关器接收机方案相比,该数字接收机能以更少的硬件资源消耗实现更高性能的接收效果。     

A circular patch antenna with parasitic element for UHF RFID applications

This article initially proposes a directly‐fed circular patch antenna with L‐shaped ground plane for Radio Frequency Identification (RFID) applications in the 900 MHz (902?928 MHz) ultrahigh frequency (UHF) band. To achieve circularly polarized (CP) radiation, two arc‐shaped notches are loaded into the main patch. To enhance the CP bandwidth so that the proposed antenna can also cover the UHF RFID band for Europe (866?869 MHz), a parasitic element is printed besides the main patch. Experimental measurements show that the 10‐dB return loss bandwidth of the proposed antenna was 30.95% (833?1138 MHz) and its corresponding 3‐dB axial ratio bandwidth was 8.95% (865?946 MHz). Good gain and radiation efficiency of more than 7 dBic and 90%, respectively, were also exhibited across the two desired UHF RFID bands. © 2015 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:681–687, 2015.     

Single‐fed broadband circularly polarized unidirectional antenna using folded plate with parasitic patch for universal UHF RFID readers

This research proposes a simple economical broadband circularly polarized antenna for universal ultra‐high frequency (UHF) RF identification (RFID) readers. The antenna utilizes a folded plate, a two‐corner truncated parasitic patch, and a ground plane. The folded plate, which is fabricated from one single plate, consists of a two‐corner truncated main patch, a wall patch, and a feed line, where the main patch is perpendicular to the wall patch, which is in turn perpendicular to the feed line. The folded plate enables currents to flow with a phase difference. The simulation results achieved an |S₁₁| < ?15 dB of 805–966 MHz (18% bandwidth), a 3‐dB axial ratio (AR) bandwidth of 834–962 MHz (14% AR bandwidth), and a gain higher than 8.6 dBic. The measured results obtained an |S₁₁| < ?15 dB of 806–970 MHz (18%), a 3‐dB AR bandwidth of 816–963 MHz (16%), and a gain greater than 7.8 dBic. The proposed antenna is applicable for universal UHF RFID readers as it covers the entire operating UHF RFID frequency range of 840–960 MHz. The parametric study and evolution of the proposed antenna are detailed in this research paper as well. © 2016 Wiley Periodicals, Inc. Int J RF and Microwave CAE 26:575–587, 2016.     

RFID阅读器相位噪声的距离相关效应研究

相位噪声是设计射频系统时的一个重要参数,它对系统性能有很大影响。对于射频识别(RFID)系统,距离相关效应对其相位噪声有重要影响。研究了无源超高频(UHF)RFID阅读器相位调制(PSK)信号的相位噪声表达式,导出距离相关效应时的相位噪声功率谱密度(PSD)和通信误符号率(SER)计算式。距离相关效应下相位噪声的测量和仿真表明,解析结果与测量、仿真结果一致。     

基于软件无线电平台的RFID被动侦测技术

随着超高频(UHF)频段射频识别(RFID)技术的广泛使用,使得RFID系统的研究者越来越关注对RFID物理层和MAC层特性的研究,以提高标签信息读取准确率、缩短读取时隙并增强协议安全性。但其前提是需要侦测及了解现有RFID协议通信过程及通信信息,获取底层数据,然而RFID阅读器只给用户提供上层结果。为解决RFID系统底层信息的获取问题,利用通用软件无线电外设被动侦测RFID系统无线通信信号,运用数字信号处理技术,设计并实现信息侦测平台。测试结果表明,该平台具有高接收灵敏度和解析准确度,UHF频段被动侦测距离最远可达8 m,优于已有侦测平台,并且对于被侦测信号的灵敏度为-115 dBm,侦测反应时间仅0.068 s,可抵抗常见无线信号干扰。     

超高频RFID系统设计与仿真

设计一种超高频的射频识别(RFID)系统结构,基于ISO/IEC18000-6协议对超高频RFID系统进行仿真。在多经衰落的环境中,实现RFID系统的收发,验证RFID系统反向散射的工作原理,得到信噪比和误码率的关系。仿真结果证明了该系统的可行性。