High-power SOI vertical DMOS transistors with lateral drain contacts: Process developments, characterization, and modeling

Silicon-on-insulator (SOI) high-power vertical double-diffused MOS (VDMOS) transistors are demonstrated with a CMOS compatible fabrication process. A new backend trench formation process ensures a defect free device layer. Scanning electron microscope micrographs show that it is nearly free of defects. This has been achieved by moving the trench formation steps toward the end of the process. Our electrical measurements indicate that the transistors are fully functional. Electrothermal simulations show that unclamped inductive switching (UIS) test involves a substantial risk of turning the parasitic bipolar transistor (BJT) on. The UIS test is used to characterize the performance of power devices under unclamped inductive loading conditions. Extreme operating condition can be expected when all the energy stored in the inductor is released directly into device. Our measurements of the fabricated SOI VDMOSFET in the static region are in good agreement with the expected impact of the self-heating on the saturation behavior. The experiments at ambient temperature of 100/spl deg/C show that the break down voltage decreases as the drain voltage increases. This indicates that a parasitic BJT has been turned on.     

Dynamics of power MOSFET switching under unclamped inductiveloading conditions

The parasitic bipolar transistor inherent in a vertical power DMOSFET structure can have a significant impact on its reliability. Unclamped Inductive Switching (UIS) tests were used to examine the reliability of DMOSFET's in extremely harsh switching conditions. The reliability of a power DMOSFET under UIS conditions is directly related to the amount of avalanche energy the device can survive. A number of DMOSFET structures were critically examined under UIS conditions to determine the impact of bipolar transistor parameters on device reliability. The UIS dynamics were studied based on the results obtained from an advanced mixed device and circuit simulator in which the internal carrier dynamics were evaluated under boundary conditions imposed by the circuit operation. It is shown that premature open base bipolar transistor breakdown can occur when the p-base sheet resistance is high. A device structure with a shallow self-aligned p⁺ region is shown to prevent the parasitic bipolar turn-on and avoid premature UIS breakdown without compromising the power-switching efficiency. The simulation results are shown to be in excellent agreement with the measured data under a wide range of inductive loading conditions     

Evaluation of the ruggedness of power DMOS transistor from electro-thermal simulation of UIS behaviour

High-voltage power MOSFETs have been widely used in switching mode power supply circuits as output drivers for industrial and automotive electronic control systems. However, as the device size is reduced, the energy handling capability is becoming a very important issue to be addressed together with the trade-off between the series on-resistance R_ON and breakdown voltage V_BR. Unclamped inductive switching (UIS) condition represents the circuit switching operation for evaluating the “ruggedness”, which characterizes the device capability to handle high avalanche currents during the applied stress. In this paper we present an experimental method which modifies the standard UIS test and allows extraction of the maximum device temperature after the applied standard stress pulse vanishes. Corresponding analysis and non-destructive prediction of the ruggedness of power DMOSFETs devices supported by advanced 2-D mixed mode electro-thermal device and circuit simulation under UIS conditions using calibrated physical models is provided also. The results of numerical simulation are in a very good correlation with experimental characteristics and contribute to their physical interpretation by identification of the mechanism of heat generation and heat source location and continuous temperature extraction.     

Scaling constraints imposed by self-heating in submicron SOIMOSFET's

The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs. The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal. Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown. The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport. The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data. Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating. Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI. For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 1.8 V. In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage. Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction     

Trade-off analysis of the p-base doping on ruggedness of SiC MOSFETs

Reliability represents a very important factor for the design of Silicon Carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs). Ruggedness of the device during abnormal operating conditions like the short circuit (SC) and avalanche conduction (during unclamped inductive switching - UIS) is an important aspect of reliability. Often, variation in design parameters to improve ruggedness during SC and UIS shows negative impact on the nominal operating performance. This paper presents a comprehensive analysis of the impact of modification of p-base doping on the performance of a 1.2 kV SiC MOSFET during SC and UIS by means of TCAD simulations. The improvement in MOSFET ruggedness by optimizing the p-base doping and its influence on the nominal operating performance is evaluated.     

Electrothermal simulations in punchthrough and nonpunchthroughIGBT's

The performance of 1200 V punchthrough (PT) and nonpunchthrough (NPT) insulated gate bipolar transistors (IGBT's) is studied in detail under unclamped inductive switching (UIS) and short circuit (SC) conditions. The need for a good physics based simulator to carry out a reliability study is pointed out in the paper. Using such a finite element-based device and circuit simulator it is shown that NPT-IGBT's show a much better performance than PT-IGBTs under UIS condition. It is also shown that an NPT device has a better short circuit withstanding capability than a PT device due to the structural differences between the two devices. As there is a huge power loss within the device during these operating conditions, device self-heating is expected to have a significant impact on device characteristics. Electrothermal simulations are used to study device self-heating and it is shown that it significantly influences device performance under SC operation whereas self-heating influences the UIS performance of only the PT device with little effect on the NPT device. The study is validated by an experimental study of short circuit failure of PT IGBTs     

功率MOS和IGBT器件在无嵌位电感开关条件下的动态雪崩特性研究

The ability of high-voltage power MOSFETs and IGBTs to withstand avalanche events under unclamped inductive switching(UIS) conditions is measured.This measurement is to investigate and compare the dynamic avalanche failure behavior of the power MOSFETs and the IGBT,which occur at different current conditions.The UIS measurement results at different current conditions show that the main failure reason of the power MOSFETs is related to the parasitic bipolar transistor,which leads to the deterioration of the avalanche reliability of power MOSFETs.However,the results of the IGBT show two different failure behaviors.At high current mode,the failure behavior is similar to the power MOSFETs situation.But at low current mode,the main failure mechanism is related to the parasitic thyristor activity during the occurrence of the avalanche process and which is in good agreement with the experiment result.     

High performance fully-depleted tri-gate CMOS transistors

Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.     

A novel UIS test system with Crowbar feedback for reduced failure energy in power devices testing

A new unclamped inductive load (UIS) test system is presented, provided with a Crowbar protection that is able to “sense” the failure of the DUT. Differently from the standard UIS test systems with a Crowbar device, this system turns on the Crowbar only when it is really needed i.e. immediately after the DUT fails during the breakdown transient. This was achieved by feeding back the DUT collector voltage to the test system control electronics. Our measurements performed on commercial power devices show that this improved UIS test system can, in the event of a failure, drastically reduce the energy dissipated on the DUT and hence its related damage effects, giving the possibility of locating the failure starting point with better accuracy and performing subsequent analyses on the damaged devices aimed to infer the failure causes.     

Fabrication of gate-all-around transistors using metal inducedlateral crystallization

Gate-all-around transistor (GAT) is demonstrated. The device can be fabricated on either a bulk silicon wafer or on the top of any device layers. The fabrication process used a new technique called metal-induced-lateral-crystallization (MILC) to recrystallize amorphous silicon to form large silicon grains in the active area. Using this technique, the transistor performance is comparable to a SOI MOSFET. Compared with the single-gate thin film transistor (SGT) and solid phase crystallization (SPC) devices, the MILC GAT has lower subthreshold slope, lower threshold voltage, higher transconductance and nearly double drive current, The impact of short channel length was investigated     

Detection of localized UIS failure on IGBTs with the aid of lock-in thermography

IGBTs with embedded current monitors, i.e. realized by separating a small part of the main device emitter and using it as the current sense terminal, are currently used to integrate intelligent power modules (IPMs). In a previous paper [Breglio G, Irace A, Napoli E, Spirito P, Hamada K, Nishijima T, et al. Study of a failure mechanism during UIS switching of planar PT-IGBT with current sense cell. Microelectron Reliab 2007;47(9–11):1756–60] we have demonstrated how, during UIS switching in particular circuit configurations, the interplay between the sense-emitter cell and the rest of the device can lead to latch-up of the lateral p–n–p bipolar transistor and current focalization in the sense-emitter cell which finally causes device failure. In this paper, we show how the location of this very localized failure spot can be very accurately determined with the aid of a very sensitive lock-in thermography setup. The main advantage of this approach is the direct applicability to the failed device without the need of time consuming sample preparation as in other failure analysis (FA) techniques.     

SOI MOSFET的失真行为

采用幂级数方法对基于全耗尽(FD)SOI MOSFET和凹陷(RC)沟道SOI MOSFET的失真行为进行了研究,发现随着沟道长度的减小失真行为变坏,且RC SOI器件较FD器件具有更好的失真行为.同时,从实验数据可以看出,不理想的体接触会由于体分布电阻的增加而使失真行为变坏.该结果可以为低失真混合信号集成系统的设计提高指导方向.     

基于全耗尽技术的SOI CMOS集成电路研究

介绍了电路的工作原理,对主要的延迟和选通控制单元及整体电路进行了模拟仿真,证明电路逻辑功能达到设计要求。根据电路的性能特点,采用绝缘体上硅结构,选用薄膜全耗尽SOICMOS工艺进行试制。测试结果表明：与同类体硅电路相比,工作频率提高三倍,静态功耗仅为体硅电路的10％,且电路的101级环振总延迟时问也仅为体硅电路的20％,实现了电路对高速低功耗的要求。     

SOI MOSFET的失真行为

采用幂级数方法对基于全耗尽(FD)SOI MOSFET和凹陷(RC)沟道SOI MOSFET的失真行为进行了研究，发现随着沟道长度的减小失真行为变坏，且RC SOI器件较FD器件具有更好的失真行为．同时，从实验数据可以看出，不理想的体接触会由于体分布电阻的增加而使失真行为变坏．该结果可以为低失真混合信号集成系统的设计提高指导方向．     

IGBT dynamics for clamped inductive switching

Clamped inductive switching performance of insulated gate bipolar transistors (IGBTs) have been studied in detail with the aid of extensive measurements and numerical simulations. Internal dynamics of a latch-up free punch-through IGBT during clamped inductive switching is studied using two-dimensional (2-D) mixed device and circuit simulations incorporating the self-heating mechanism. Failure of IGBT during inductive load turn-off is shown to occur due to thermally assisted carrier multiplication at the reverse biased p-base n-drift region junction under the emitter contact     

Optimization of oxygen-implanted silicon substrates for CMOS devices by electrical characterization

The use of oxygen-implanted silicon substrates for CMOS SOI device technology has great potential for use in VLSI and radiation-hardened circuits. The electrical characterization of such substrates is described by reference to CMOS devices fabricated directly into them; no epitaxial silicon was grown. Electrical parameters were related to the oxygen-implantation conditions of dose and temperature. Thermally generated oxygen donors in the top silicon layer were identified as being responsible for threshold voltage shifts and resistivity changes that altered transistor characteristics. Suitable boron implants enabled electrical parameter control to be maintained. Full island-to-substrate electrical isolation was only achieved for oxygen doses greater than 1.6 × 10¹⁸cm^-2, a larger dose from that required to create stoichiometric SiO2. Channel mobilities and NMOS back-channel leakage currents were found to be dependent on oxygen implant temperature; as a result a favorable implant window of 460-510 °C was established to fabricate ring oscillators twice as fast as bulk silicon counterparts for the same power dissipation.     

Avalanche behavior of power MOSFETs under different temperature conditions

The ability of high-voltage power MOSFETs to withstand avalanche events under different temperature conditions are studied by experiment and two-dimensional device simulation.The experiment is performed to investigate dynamic avalanche failure behavior of the domestic power MOSFETs which can occur at the rated maximum operation temperature range(-55 to 150℃).An advanced ISE TCAD two-dimensional mixed mode simulator with thermodynamic non-isothermal model is used to analyze the avalanche failure mechanism.The unclamped inductive switching measurement and simulation results show that the parasitic components and thermal effect inside the device will lead to the deterioration of the avalanche reliability of power MOSFETs with increasing temperature.The main failure mechanism is related to the parasitic bipolar transistor activity during the occurrence of the avalanche behavior.     

VDMOS管的特性及在电子镇流器中的应用

本文主要介绍VDMOS管的制造工艺与结构,并将VDMOS管的特性与双极晶体管作比较,突出了VDMOS管在电子镇流器中作为开关管的优势,对VD－MOS管在电子镇流器中的具体使用条件作了说明。