超薄栅MOS器件热载流子应力下SILC的产生机制

通过测量界面陷阱的产生,研究了超薄栅n MOS和p MOS器件在热载流子应力下的应力感应漏电流( SIL C) .在实验结果的基础上,发现对于不同器件类型( n沟和p沟)、不同沟道长度( 1、0 .5、0 .2 75和0 .13 5 μm)、不同栅氧化层厚度( 4和2 .5 nm) ,热载流子应力后的SIL C产生和界面陷阱产生之间均存在线性关系.这些实验证据表明MOS器件减薄后,SIL C的产生与界面陷阱关系非常密切     

超深亚微米LDD nMOSFET中的非幸运电子模型效应

通过对采用0.18μm CMOS工艺制造的两组不同沟道长度和栅氧厚度的LDD器件电应力退化实验发现,短沟薄栅氧LDD nMOSFET(Lg=0.18μm,Tox=3.2nm)在沟道热载流子(CHC)应力下的器件寿命比在漏雪崩热载流子(DAHC)应力下的器件寿命要短,这与通常认为的DAHC应力(最大衬底电流应力)下器件退化最严重的理论不一致.因此,这种热载流子应力导致的器件退化机理不能用幸运电子模型(LEM)的框架理论来解释.认为这种"非幸运电子模型效应"是由于最大碰撞电离区附近具有高能量的沟道热电子,在Si-SiO2界面产生界面陷阱(界面态)的区域,由Si-SiO2界面的栅和漏的重叠区移至沟道与LDD区的交界处以及更趋于沟道界面的运动引起的.     

超深亚微米LDD nMOSFET中的非幸运电子模型效应

通过对采用0.18μm CMOS工艺制造的两组不同沟道长度和栅氧厚度的LDD器件电应力退化实验发现，短沟薄栅氧LDD nMOSFET（Lg=0.18μm，Tox=3.2nm）在沟道热载流子(CHC)应力下的器件寿命比在漏雪崩热载流子（DAHC）应力下的器件寿命要短，这与通常认为的DAHC应力（最大衬底电流应力）下器件退化最严重的理论不一致．因此，这种热载流子应力导致的器件退化机理不能用幸运电子模型（LEM）的框架理论来解释．认为这种“非幸运电子模型效应”是由于最大碰撞电离区附近具有高能量的沟道热电子，在Si-SiO2界面产生界面陷阱(界面态)的区域，由Si-SiO2界面的栅和漏的重叠区移至沟道与LDD区的交界处以及更趋于沟道界面的运动引起的．     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化.实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流(SILC)的退化和Vth的退化均存在线性关系.为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化. 实验结果表明,在不同直接隧穿应力过程中,应力感应漏电流（SILC）的退化和Vth的退化均存在线性关系. 为了解释直接隧穿应力下SILC的起因,建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.     

热载流子诱生MOSFET/SOI界面陷阱的正向栅控二极管技术表征

本文完成了热载流子诱生MOSFET/SOI界面陷阱正向栅控二极管技术表征的实验研究 .正向栅控二极管技术简单、准确 ,可以直接测得热载流子诱生的平均界面陷阱密度 ,从而表征器件的抗热载流子特性 .实验结果表明 :通过体接触方式测得的MOSFET/SOI栅控二极管R G电流峰可以直接给出诱生的界面陷阱密度 .抽取出来的热载流子诱生界面陷阱密度与累积应力时间呈幂指数关系 ,指数因子约为 0 787     

新的正向栅控二极管技术分离热载流子应力诱生SOI NMOSFET界面陷阱和界面电荷的研究

报道了用新的正向栅控二极管技术分离热载流子应力诱生的SOI-MOSFET界面陷阱和界面电荷的理论和实验研究.理论分析表明:由于正向栅控二极管界面态R-G电流峰的特征,该峰的幅度正比于热载流子应力诱生的界面陷阱的大小,而该峰的位置的移动正比于热载流子应力诱生的界面电荷密度. 实验结果表明:前沟道的热载流子应力在前栅界面不仅诱生相当数量的界面陷阱,同样产生出很大的界面电荷.对于逐渐上升的累积应力时间,抽取出来的诱生界面陷阱和界面电荷密度呈相近似的幂指数方式增加,指数分别为为0.7 和0.85.     

新的正向栅控二极管技术分离热载流子应力诱生SOI NMOSFET界面陷阱和界面电荷的研究

报道了用新的正向栅控二极管技术分离热载流子应力诱生的SOI-MOSFET界面陷阱和界面电荷的理论和实验研究.理论分析表明:由于正向栅控二极管界面态R-G电流峰的特征,该峰的幅度正比于热载流子应力诱生的界面陷阱的大小,而该峰的位置的移动正比于热载流子应力诱生的界面电荷密度. 实验结果表明:前沟道的热载流子应力在前栅界面不仅诱生相当数量的界面陷阱,同样产生出很大的界面电荷.对于逐渐上升的累积应力时间,抽取出来的诱生界面陷阱和界面电荷密度呈相近似的幂指数方式增加,指数分别为为0.7 和0.85.     

热载流子诱生MOSFET／SOI界面陷阱的正向机控二极管技术表征

本文完成了热载流子诱生MOSFET/SOI界面陷阱正向栅控二极管技术表征的实验研究。正向栅控二极管技术简单、准确，可以直接测得热载流子诱生的平均界面陷阱密度，从而表征器件的抗热载流子特性。实验结果表明：通过体接触方式测得的MOSFET/SOI栅控二级管R-G电流峰可以直接给出诱生的界面陷阱密度。抽取出来的热载流子诱生界面陷阱密度与累积应力时间呈幂指数关系，指数因子约为0.787。     

HfO2高k栅介质漏电流机制和SILC效应

利用室温下反应磁控溅射的方法在p-Si(100)衬底上制备了HfO2栅介质层,研究了HfO2高k栅介质的电流传输机制和应力引起泄漏电流(SILC)效应.对HfO2栅介质泄漏电流输运机制的分析表明,在电子由衬底注入的情况下,泄漏电流主要由Schottky发射机制引起,而在电子由栅注入的情况下,泄漏电流由Schottky发射和Frenkel-Poole发射两种机制共同引起.通过对SILC的分析,在没有加应力前HfO2/Si界面层存在较少的界面陷阱,而加上负的栅压应力后在界面处会产生新的界面陷阱,随着新产生界面陷阱的增多,这时在衬底注入的情况下,电流传输机制就不仅仅是由Schottky发射机制引起,而存在Frenkel-Poole发射机制起作用.同时研究表明面积对SILC效应的影响很小.     

SILC-related effects in flash E2PROM's-Part I: Aquantitative model for steady-state SILC

In this paper a quantitative model for the steady-state component of the stress induced leakage current (SILC) is developed. The established model is based on the observation of basic degradation monitors on conventional, thermal SiO₂ gate dielectrics in the thickness range of 6.8-7.1 nm. From a systematic, experimental study, it has been found for the first time that the steady-state SILC, observed after a wide range of constant current stress (CCS) conditions (gate injection polarity), can be uniquely described by a simple, semi-empirical relation, which consists of two parts: 1) the dependence on the measurement field is described as Fowler-Nordheim (FN) tunneling through an oxide barrier of reduced but fixed height (i.e., 0.9 eV), and 2) the level of the SILC at a fixed oxide field is given by the density of neutral bulk oxide traps. Except for a calibration, depending on the oxide thickness and processing, no model parameters have to be adjusted in order to describe all our data. Also, based on bake experiments it has been concluded that interface traps are not causally related to the steady-state SILC in spite of the linear relation which exists between both. Furthermore, these bake experiments provide new evidence that bulk oxide traps play a crucial role in the SILC conduction mechanism     

On stress induced leakage current in 5 and 3 nm thick oxides

The stress induced leakage current (SILC) in Si/SiO₂ structures with thin gate oxides has a steady-state component which increases drastically when the oxide thickness decreases. It is generally agreed that the SILC is due to electron tunnelling trough stress-induced traps. However, it was observed that the SILC, created by Fowler–Nordheim injection, decays continuously when, after stress, the samples are positively or negatively biased at a low voltage. The decay is irreversible as long as the gate oxide is not biased at a high voltage. The present article adds complementary observations. It shows, first that the above phenomenon is observed in 3.5 nm thick oxides, secondly, that this phenomenon is stable as long as the temperature stays below 200°C, and thirdly, that during the SILC decay, the interface state density does not diminish.     

HfO_2高k栅介质漏电流机制和SILC效应

利用室温下反应磁控溅射的方法在 p- Si(1 0 0 )衬底上制备了 Hf O2 栅介质层 ,研究了 Hf O2 高 k栅介质的电流传输机制和应力引起泄漏电流 (SIL C)效应 .对 Hf O2 栅介质泄漏电流输运机制的分析表明 ,在电子由衬底注入的情况下 ,泄漏电流主要由 Schottky发射机制引起 ,而在电子由栅注入的情况下 ,泄漏电流由 Schottky发射和 Frenkel-Poole发射两种机制共同引起 .通过对 SIL C的分析 ,在没有加应力前 Hf O2 / Si界面层存在较少的界面陷阱 ,而加上负的栅压应力后在界面处会产生新的界面陷阱 ,随着新产生界面陷阱的增多 ,这时在衬底注入的情况下 ,电流传     

Two types of neutral electron traps generated in the gate silicon dioxide

Electron trap generation in the gate oxide is a severe problem for the reliability of MOS devices, since it can cause stress-induced leakage current (SILC) and eventually lead to oxide breakdown. Although much effort has recently been made to understand the mechanism for the trap generation, the properties of the generated traps have received relatively less attention. The objective of this paper is to present unambiguous results, showing that two different types of neutral electron traps can be created by the same stress and to compare the properties of these two types of traps. Differences have been found in terms of their generation kinetics, trap filling, detrapping, and refilling after detrapping. The results also indicate that the energy levels of these two types of traps are different.     

Trap generation and breakdown processes in very thin gate oxides

Neutral electron traps are generated in gate oxide during electrical stress, leading to degradation in the form of stress-induced leakage current (SILC) and eventually resulting in breakdown. SILC is the result of inelastic, trap-assisted tunneling of electrons that originate in the conduction band of the cathode. Deuterium annealing experiments call into question the interfacial hydrogen release model of the trap generation mechanism. A framework for modeling time-to-breakdown is presented.     

On the SILC mechanism in MOSFET’s with ultrathin oxides

In this paper, n-channel MOSFET’s with oxides 1.2, 1.5 and 1.8 nm thick are studied. In such devices the trap assisted tunnelling (TAT) current required to fit the gate current vs. gate voltage, I_g(V_g), characteristics is thought to flow through Si–SiO₂ interface traps. After stress, it becomes a stress induced leakage current (SILC) which should allow to obtain interface trap density variations with stress. The TAT mechanism is discussed. Then, the Si–SiO₂ interface trap densities extracted using the SILC and charge pumping (CP) are compared. Much larger trap creation rates are viewed by the SILC with regard to CP, questioning the occurrence of the SILC through interface traps. To answer this question the interaction between SILC and CP measurements is investigated.     

Total dose dependence of radiation-induced leakage current in ultra-thin gate oxides

Radiation-induced leakage current (RILC) has been studied on ultra-thin gate oxides (4 and 6 nm) irradiated with 8 MeV electrons. Both RILC and stress-induced leakage current (SILC) have been fitted with the same Fowler–Nordheim law, suggesting that RILC and SILC have similar conduction mechanisms. The RILC dependence from total dose during irradiation has been analysed and compared with the SILC dependence from the cumulative injected charge. Different growth laws of RILC and SILC have been found in the two cases. The intensity of positive and negative RILC also depends on the applied gate bias voltage during irradiation, probably reflecting different distributions of the oxide traps mediating the trap assisted tunnelling. Finally, we have presented the first evidence of a quasi-breakdown phenomenon due to ionizing radiation.     

利用直接隧穿弛豫谱技术对超薄栅MOS结构中栅缺陷的研究

给出了超薄栅MOS结构中直接隧穿弛豫谱(DTRS)技术的细节描述,同时在超薄栅氧化层(＜3nm)中给出了该技术的具体应用.通过该技术,超薄栅氧化层中明显的双峰现象被发现,这意味着在栅氧化层退化过程中存在着两种陷阱.更进一步的研究发现,直接隧穿应力下超薄栅氧化层(＜3nm)中的界面/氧化层陷阱的密度以及俘获截面小于FN 应力下厚氧化层(＞4nm)中界面/氧化层陷阱的密度和俘获截面,同时发现超薄氧化层中氧化层陷阱的矩心更靠近阳极界面.