局部化混合晶向应变硅CMOS结构及其制备方法

描述了混合晶向技术原理以及各种硅衬底晶向的反型层中载流子迁移率特性,分析了应变硅技术对载流子迁移率的增强机理,介绍了DSL这种应变硅技术的工艺实现方法。提出了将混合晶向技术和应变硅技术两者有机结合以提高载流子迁移率的局部化混合晶向应变硅基本思路,分析了基于该基本思路的局部化混合晶向应变硅CMOS结构及其电学性能。最后详细描述了局部化混合晶向应变硅CMOS结构工艺流程,为开发高性能、低功耗CMOS集成电路提供了一个科学合理的工艺制备方法。     

双轴压应力Ge材料价带物理参量计算

应变Ge材料载流子迁移率高,且与硅工艺兼容,在硅基CMOS中的应用潜力大。能带结构是深入研究应变Ge材料基本属性,设计高速/高性能CMOS器件的重要理论依据。为此,本文采用结合形变势理论的kp微扰法,分析了(001)双轴压应力Ge材料价带结构、轻重空穴带Γ点能级及轻重空穴带间分裂能等价带物理参量与应力的理论关系,获得有实用价值的相关结论。     

延续摩尔定律的新材料——应变Si

介绍了应变Si材料的需求背景和必要性.阐述了在MOS器件中使用衬底致双轴应变后器件性能的改善,在总结了与工艺致单轴应变相比衬底致双轴应变的不足以及工艺致单轴应变的优势之后,讲述了基于SiGe源漏和基于双应力线的两种工艺致单轴应变技术及其对MOS器件性能的提高.简单介绍了国际上近年来对应变Si材料与器件的研究发展状况和应变Si技术达到的各种水平,以及国内对应变Si的研究状况,并对应变Si技术的使用优势和应用前景做了简单分析.     

纳米CMOS电路的应变Si衬底制备技术

应变硅衬底材料——弛豫SiGe层作为应变硅技术应用的基础,其质量的好坏对应变硅器件性能有致命的影响。综述了近年来用于纳米CMOS电路的各类弛豫SiGe层的制备技术,并对弛豫SiGe层中应变测量技术进行了简单的介绍,以期推动应变硅技术在我国芯片业的应用。     

基于SGOI和CESL结构的新型应变硅NMOSFET的有限元研究

应变硅技术通过在沟道区引入适当的应变,达到提高载流子迁移率、改善MOS器件性能的目的.利用有限元法,研究了一种基于SGOI与氮化硅CESL应变结构的新型应变硅NMOSFET.结果表明,与采用单一的SGOI或CESL结构相比,两者共同作用下的新结构能更有效地提高沟道应变.增加氮化硅薄膜的本征应力、减小应变硅层厚度、适当提高锗组分,均能有效增加硅沟道区的应变量.采用有限元分析进行的模拟研究,可弥补实验测量的不足,为纳米级应变硅器件的设计和制造提供参考.     

应变硅电子迁移率解析模型

提出了一个应变硅沟道电子迁移率解析模型.模型以应变张量为对象研究应变硅沟道电子迁移率,因此与工艺相独立;适用于施加双轴应力及<100>/<110>方向单轴应力,沟道方向为<100>/<110>的器件;易于嵌入常用仿真工具中.     

应变硅电子迁移率解析模型

提出了一个应变硅沟道电子迁移率解析模型.模型以应变张量为对象研究应变硅沟道电子迁移率,因此与工艺相独立;适用于施加双轴应力及<100>/<110>方向单轴应力,沟道方向为<100>/<110>的器件;易于嵌入常用仿真工具中.     

体硅CMOS FinFET结构与特性研究

建立在SOI衬底上的 FinFET结构被认为是最具全面优势的非常规MOS器件结构.本文通过合理的设计将FinFET结构迁移到普通体硅衬底上,利用平面凹槽器件的特性解决了非绝缘衬底对器件短沟道效应的影响,同时获得了一些标准集成电路工艺上的改进空间.运用标准CMOS工艺实际制作的体硅CMOS FinFET器件获得了较好的性能结果并成功地集成到CMOS反相器和环形振荡器中.结构分析与实验结果证明了体硅CMOS FinFET在未来电路中的应用前景.     

应变硅n-MOSFET中电子迁移率的增强及其温度特性

采用减压化学气相淀积(RPCVD)技术在弛豫Si_(1-x)Ge_x虚拟衬底上赝晶生长应变硅层,以其为沟道材料制造得到的应变硅n-MOSFET表现出显著的性能提升。研究了通过改变Si_(1-x)Ge_x中Ge的摩尔组分x以改变硅帽层中的应变以及在器件制造流程中通过控制热开销来避免应变硅层发生弛豫等关键问题。在室温下,相对于体硅器件,应变硅器件表现出约87%的低场电子有效迁移率增强,在相同的过驱动电压下,饱和漏端电流增强约72%。在293 K到353 K的温度范围内研究了反型层电子有效迁移率和饱和漏端电流随温度的变化,实验结果表明,当温度升高时应变硅材料的电子迁移率增强倍数保持稳定。     

基于SiGe虚拟衬底的低场迁移率提升140%的应变Si沟道NMOS器件 Cui Wei(崔伟)1,2,Tang Zhaohuan(唐昭焕)2, Tan Kaizhou(谭开洲)2, Zhang Jing(张静)2,

本文研究了一种应变SiGe沟道的NMOS器件,通过调整硅帽层、SiGe缓冲层,沟道掺杂和Ge组分变化,并采用变能量硼注入形成P阱的方式,成功完成了应变NMOS器件的制作。测试结果表明应变的NMOS器件在低场(Vgs=3.5V, Vds=0.5V)条件下,迁移率极值提升了140%,而PMOS器件性能保持不变。文中对硅基应变增强机理进行了分析。并利用此NMOS器件研制了一款CMOS倒向器,倒向器特性良好, 没有漏电,高低电平转换正常。     

具有应变沟道及EOT 1.2nm高性能栅长22nm CMOS器件

深入研究了亚30nm CMOS关键工艺技术，特别是提出了一种新的低成本的提高空穴迁移率的技术--Ge预非晶化S/D延伸区诱生沟道应变技术，它使栅长90nm pMOS空穴有效迁移率在0.6MV/cm电场下提高32%. 而且空穴有效迁移率的改善，随器件特征尺寸缩小而增强. 利用零阶劳厄线衍射的大角度会聚束电子衍射分析表明，在沟道区相应的压应变为-3.6%. 在集成技术优化的基础上，研制成功了高性能栅长22nm应变沟道CMOS器件及栅长27nm CMOS 32分频器电路（其中分别嵌入了57级/201级环形振荡器）, EOT为1.2nm,具有Ni自对准硅化物.     

硅基集成光电子器件的新进展

综述了硅基微纳激光器、调制器、探测器及光传输控制器件的最新研究进展.重点阐述了表面等离子体、量子阱、光子晶体及纳米光栅等新型结构在提高器件综合性能和降低器件尺寸方面的重大作用.同时,还展示了用标准互补金属氧化物半导体(CMOS)技术,实现硅基光子器件和电子器件在同一基片上微纳集成的巨大前景.     

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.     

Deep submicron CMOS based on silicon germanium technology

The advantages to be gained by using SiGe in CMOS technology are examined, Conventional MOSFETs are compared with SiGe heterojunction MOSFETs suitable for CMOS technology and having channel lengths between 0.5 and 0.1 μm. Two-dimensional computer simulation demonstrates that the improved mobility in the SiGe devices, due to higher bulk mobility and the elimination of Si/SiO₂ interface scattering by the inclusion of a capping layer, results in significant velocity overshoot close to the source-end of the channel. The cut-off frequency, f_t , is found to increase by around 50% for n-channel devices while more than doubling for p-channel devices for typical estimates of mobility. The results offer the prospect of a more balanced CMOS and improved circuit speed especially when using dynamic logic     

High-performance strained-SOI CMOS devices using thin film SiGe-on-insulator technology

We have developed high-performance strained-SOI CMOS devices on thin film relaxed SiGe-on-insulator (SGOI) substrates with high Ge content (25%) fabricated by the combination of separation-by-implanted-oxygen (SIMOX) and internal-thermal-oxidation (ITOX) techniques without using SiGe buffer structures. The maximum enhancement of electron and hole mobilities of strained-SOI devices against the universal mobility amounts to 85 and 53%, respectively. On the other hand, we have also observed the reduction of carrier mobility in a thinner strained-Si layer or at higher vertical electric field conditions. For the first time, we have demonstrated a high-speed CMOS ring-oscillator using strained-SOI devices, and its improvement amounts to 63% at the supply voltage of 1.5 V, compared to control-SOI CMOS.     

高k栅介质原子分辨率的电镜表征：研究进展和展望

随着特征尺寸不断缩小,CMOS器件已步入纳米尺度范围,因此纳米尺度器件的结构表征变得尤为关键。完备的半导体器件结构分析,要求确定原子位置、局部化学元素组成及局域电子结构。高分辨（分析型）透射电镜及其显微分析技术,能够提供衍衬像（振幅衬度像）、高分辨像（相位衬度像）、选区电子衍射和会聚束电子衍射、X射线能谱（EDS）及电子能量损失谱（EELS）等分析手段,已作为半导体器件结构表征的基本工具。配有高角度环形暗场探测器的扫描透射电镜（STEM）,因其像的强度近似正比于原子序数（Z）的平方,它可在原子尺度直接确定材料的结构和化学组成。利用Z-衬度像配合高分辨电子能量损失谱技术,可确定新型CMOS堆垛层中的界面结构、界面及界面附近的元素分布及化学环境。近年来新开发的球差校正器使得HRTEM／STEM的分辨率得到革命性提高（空间分辨率优于0．08nm,能量分辨率优于0．2eV）,在亚埃尺度上实现单个纳米器件的结构表征。装备球差校正器的新一代HRTEM和STEM,使得高k栅介质材料的研究进入一个新时代。本文首先介绍了原子分辨率电镜（HRTEM和STEM）的基本原理和关键特征,对相关高分辨谱分析技术（如EDS和EELS）加以比较;然后综述了HRTEM／STEM在高k栅介质材料（如铪基氧化物、稀土氧化物和外延钙钛矿结构氧化物）结构表征方面的最新进展;最后对亚埃分辨率高k栅介质材料的结构表征进行了展望。     

Fully symmetric cooled CMOS on (110) plane

A cooled CMOS device using dual-polysilicon gates, (110) Si substrates, lightly doped drains with doping concentrations of 10¹⁴ cm^-2, and no channel implant is described. It is found that the peak mobility of a p⁺ polysilicon gate pMOS transistor on a (110) plane is 1.6 times larger than that on a (100) plane at 77 K. This pMOS transistor si very promising for use at 77 K because of its steeper subthreshold slope and higher hole mobility. The design has realized fully symmetrical cooled CMOS devices with 0.8-μm gates in which saturation currents and transductances of both n and pMOS transistors have been almost equalized. This fully symmetric cooled CMOS increases the ring oscillator speed by a factor of 1.2 and allows flexible CMOS circuit design that allows effective use of NOR gates     

On the number of fast interface states of standard CMOStechnologies

In recent publications about MOS devices, a fast interface state (IS) density has been found for standard thermal oxides, which is much higher than previously expected. This high number of fast interface states was shown to have a strong impact on the effective mobility in state of-the-art MOSFET's with high channel doping concentrations. This calls into question the validity of the standard procedure for mobility data extraction and of all device simulations in which fast interface states are neglected. In contrast to those results our investigations of standard MOS devices fabricated by three different manufactures do not yield such a high interface state density. Our results show that fast interface states can still be neglected for modeling state-of-the-art CMOS technologies and previously extracted mobility data are still valid although fast interface states have been ignored     

固态微波毫米波、太赫兹器件与电路的新进展

固态微波毫米波、太赫兹器件与电路是微电子、纳电子领域的战略制高点之一,SiCMOS技术进入纳米加工时代,GaAs,InP材料的"能带工程"(超晶格、异质结),GaN材料的宽禁带和界面特性以及石墨烯纳米级新材料的创新发展都深刻影响着固态微波毫米波、太赫兹器件与电路的进展。描述了固态微波、毫米波和太赫兹器件与电路当前发展的新亮点,包括纳米加工技术、石墨烯新材料、GaN MMIC功率合成突破3 mm频段百瓦级、三端器件进入太赫兹和两端器件倍频链突破2.7 THz微瓦功率。并重点就当前发展的RF CMOS,SiGe HBT,LDMOS,GaAsPHEMT,GaAs MHEMT,InP HEMT,InP HBT,GaN HEMT,GFET和THz倍频链等10个领域的发展特点、2011年最新发展以及未来发展趋势进行介绍。