射频宽带低噪声放大器设计

介绍了射频宽带放大器的设计原理及流程。设计实现的射频宽带低噪声放大器,采用分立器件和微带线匹配,选用Agilent公司生产的低噪声增强赝配高电子迁移率晶体管ATF-551M4,用ADS软件进行设计、仿真和优化,实现了在1.1GHz～2.2GHz范围内,增益24dB以上,噪声系数小于1.2dB的两级宽带低噪声放大器设计。由于设计频带覆盖了多个通信常用频点,因此决定此低噪声放大器的应用会十分广泛。最后利用ProtelDXP软件对电路进行了版图设计,并在FR4基板上实现了该设计,给出了实测结果。     

Smith圆图辅助设计低噪声宽频带放大器

接收微弱射频信号需要研究低噪声放大器的设计,文中在分析传统低噪声放大器设计的基础上引入对放大器匹配电路品质因数,扩宽放大器的频带;通过加入电流负反馈及在负载端并联电阻,提高放大器的稳定性、降低放大器驻波比,得到宽频带低噪声放大器的设计方法.仿真结果表明设计的放大器工作绝对稳定.     

低噪声放大器的ADS仿真与设计

介绍了利用ADS仿真软件设计低噪声放大器的方法及主要步骤,晶体管选择低噪声、价格便宜但性能优良的AT-41511。使用ADS器件库中的sp模型,重点进行了输入和输出匹配电路的设计。该低噪声放大器工作在750～850MHz的频段内,实际的测试结果噪声系数小于1.8dB,增益大于14dB,表明放大器达到了预设的技术指标,性能良好,可用于射频接收机前端。通过设计过程可以看出,利用ADS进行射频微波电路仿真,可以很方便地得出最佳电路设计,且指标完全符合要求。     

低噪声放大器的网络设计研究

本文就设计低噪声放大器的方法进行了研究分析。首先对低噪声放大器的特点进行了介绍,还介绍了低噪声放大器的网络组成和性能指标,最后本文用网络匹配法来设计低噪声放大器,并应用Ansoft公司的Designer软件包通过模拟集成电路国家重点实验室高频双极晶体管模型进行了设计分析。这种应用SmithTool工具、通过网络匹配的方法来设计电路更加方便快捷,且能符合工业基本要求。     

有问必答

<正>卫星电视高频头问答问1:高频头由哪几部分组成?它的作用是什么?答:高频头(LNB)又称低噪声放大变频器,安装在卫星电视接收天线上,属室外单元。它由波导微带转换器、微波低噪声宽带放大器、微波混频器、第一本振和第一中频前置放大器组成。     

超宽带高线性低噪声放大器的研制

随着雷达技术以及现代移动通讯的不断发展,系统对低噪声放大器的带宽、线性、低噪声提出了更高的要求.一个性能良好的低噪声放大器可大大改善接收机系统的信噪比.本文从宽带匹配和噪声的角度出发分析了超宽带高线性低噪声放大器的设计,利用ADS软件的辅助设计,实现了一种在30MHz-1350MHz频段的高线性低噪声放大器.通过采用视...     

P波段低温低噪声放大器的设计与测量

本文介绍了用于P波段高温超导滤波系统的低温低噪声级联放大器的研制以及低温系统调谐方法和测试方法。低噪声放大器采用Agilent ATF-54143高电子迁移率场效应晶体管,集总参数元件进行设计,引入源级负反馈与有耗电阻提高稳定性,选用П型输入匹配网络,扩展带宽,满足直流偏置的要求。制备的低温低噪声放大器在70K温度下,工作频段为450-550MHz,两级放大电路噪声低于0.5dB,输入驻波比优于1.3,增益29.2±0.3dB。采用了两极供电系统以方便在70K的条件下对滤波系统进行调节,使得前级滤波器和低噪声放大器获得较好匹配,最终系统输入驻波比优于1.3,增益27±0.1dB,带宽15MHz,系统噪声小于0.6dB。     

低频μV信号放大器的设计与制作

本文在对多级放大噪声系数理论分析讨论的基础上,介绍了一种低噪声μV信号放大器的设计与制作。该放大器的前置放大器由分立元件构成。滤波部分采用切换电容的方法分频段滤波,实现不同频段的选频放大。文章最后对实际制作出的放大器给出了测试结果,并对结果做出分析。     

5.2 GHz 0.18 μm CMOS集成低噪声放大器设计

低噪声放大器是无线通讯系统接收机前端的核心部件.本文采用TSMC 0.18 m CMOS工艺,设计工作在5.2 GHz的单端cascode和差分cascode两种结构的低噪声放大器(LNA).本设计利用Agilent公司的Advanced Design System(ADS)软件对电路进行设计优化,通过对两种结构的低噪声放大器性能参数进行比较,发现为达到相同的性能指标,单端LNA会引入不确定的寄生电感,从而破坏电路的输入匹配.而差分LNA能够完全避免这种现象,并且能够有效抑制直流漂移,同时对共模扰动影响具有很强的的抑制能力.所以,差分cascode结构成为目前低噪声放大器设计的首选.     

激光回波小信号宽带放大器设计

设计了一款激光回波小信号宽带低噪声放大器。选用低噪声、高带宽电流反馈型差分运算放大器THS4509,采用两级放大电路结构以获得较大的放大倍数,利用传输线变压器实现输出信号由双端到单端转换。为减小噪声,采用过渡带特性最好的椭圆低通滤波器滤除带外噪声。经实验验证,该放大器具有40 dB放大倍数、120 MHz带宽和小于10 mV(pp)的系统噪声,能对各种反射率条件下不同目标反射回的微弱激光小信号进行有效放大,较好地解决了远距离和低反射率目标物体测距问题,实际测试测距量程可达450 m。     

A 0.6‐V sub‐mW X‐band RFSOI CMOS LNA with novel complementary current‐reused technique

A fully integrated 0.6 V low‐noise amplifier (LNA) for X‐band receiver application based on 0.18 μm RFSOI CMOS technology is presented in this paper. To achieve low noise and high gain with the constraint of low voltage and low power consumption, a novel modified complementary current‐reused LNA using forward body bias technique is proposed. A diode connected MOSFET forward bias technique is employed to minimize the body leakage and improve the noise performance. A notch filter isolator is constructed to improve the linearity of low voltage. The measured results show that the proposed LNA achieves a power gain of 11.2 dB and a noise figure of 3.8 dB, while consuming a DC current of only 1.6 mA at supply voltage of 0.6 V. Copyright © 2017 John Wiley & Sons, Ltd.     

0.03～4.5GHz超宽带低噪声放大器设计与实现

采用负反馈和均衡器结构,选用Avago公司生产的增强型高电子迁移率晶体管ATF55143,利用ADS软件设计、仿真和优化,最终实现了一款覆盖0.03~4.5 GHz频段的低噪声放大器,该模块中的低噪声放大器使用分立元件搭建,匹配电路调试灵活,满足了模块对输入输出驻波的高要求。其增益大于25 d B,平坦度小于等于±0.9 d B,噪声系数小于1.2 d B,输入输出驻波比小于1.75。该放大器模块体积小巧,成本较低,调试灵活,可望在通讯领域得到广泛应用。     

双平衡支路低噪声放大器的设计与测试

本文通过使用ADS软件平台,设计了一种双平衡支路低噪声放大器(LNA),并设计、加工了实验样板进行测试。双平衡支路LNA是通过在输入和输出端分别加入3dB耦合器对输入信号进行分流、合并来提高性能的。3dB耦合器和晶体管之间还要设计阻抗匹配网络以减小信号的衰减。仿真结果表明LNA完全满足系统要求的性能指标。而测试过程中,由于实验样板中的无源元件并非仿真中所用的品牌贴片元件(比如,松下、TDK的器件),所以元件的寄生效应引起的阻抗失配和LC谐振导致了系统的性能在一定程度上的下降,但总体仍基本满足要求。这些问题可以通过使用品牌元件和调节元件值来解决。     

Design of 3.1 to 10.6 GHz ultra‐wideband flat gain LNA

In this paper, a new ultra‐wideband low‐noise amplifier (LNA) is proposed. The proposed LNA has flat gain and low noise figure (NF) in the frequency range of 3.1 to 10.6 GHz. To obtain higher gain, cascode architecture is used. In this design, to have a lower NF, the noise cancellation technique applies to the cascode architecture. In addition, to have better matching at the input and output, active feedback and matching transistors are used, which also leads to better NF. To have flat gain, RLC load is used. In the proposed LNA, only one inductor is used, which leads to the smaller chip area. The proposed circuit is designed in 90 nm CMOS technology. The simulation shows NF of between 1.62 and 2.1 dB, flat gain between 11.9 and 12 dB and power consumption of 11.72 mW in the frequency range of 3.1 to 10.6 GHz. The simulation results support the theoretical predictions. Copyright © 2017 John Wiley & Sons, Ltd.     

射频低噪声放大器电路结构设计

文中介绍三种射频LNA的电路结构。inductivedegeneratecascode结构具有很好隔离度、低噪声及高增益而普遍使用,在此基础上介绍高稳定度的LNA结构和低功耗的偏置电流复用结构。     

A common‐gate common‐source low noise amplifier based RF front end with selective input impedance matching for blocker‐resilient receivers

This paper presents an integrated wideband radio frequency front end with improved blocker resilience achieved through selective voltage attenuation at both input and output nodes of the low noise amplifier (LNA). The architecture differs from traditional LNA architectures where blockers are only attenuated at LNA output node. The proposed dual attenuation is attained by designing a low intrinsic input impedance common‐gate common‐source LNA with capacitive feedback, together with an N‐path filtering load. The capacitive feedback across the LNA ensures that the selective N‐path filtering profile at the LNA output is transferred to the LNA input nodes creating a selective input impedance. Consequently, the achieved front‐end input impedance is low at blocker frequencies and matched to the source impedance at the desired frequencies, creating the desired voltage attenuation for blockers. Further, a detailed theoretical analysis of proposed architecture is presented, which leads to clear design guidelines. Evaluated in a 28‐nm fully depleted silicon‐on‐insulator complementary metal oxide semiconductor (CMOS) process, front end is designed for wideband operation from 0.7 to 2.7 GHz. It consumes 11‐mA current from a 1‐V supply (excluding local oscillator (LO) buffering) and possesses a maximum noise figure of 5.1 dB. The front end demonstrates an out‐of‐band blocker compression point of ?1.5 dBm and out‐of‐band IIP3 of +14 dBm at a 100‐MHz offset from LO frequency. In comparison with a traditional common‐gate common‐source LNA‐based front end with wideband input impedance matching, the proposed front end achieves 3.5‐dB improvement in the blocker compression point at a 100‐MHz offset from LO.     

ANN modeling for design of a matched low noise pHEMT amplifier for mobile application

For high quality performance, future efficient wireless communication systems require a Broadband Amplifier in the frequency range under consideration. When such an amplifier is plugged into the measuring path it would enable the system to perceive even the weakest of signals. To achieve this, a new Scattering-parameter model that is valid for a wide frequency range has been developed for microwave analysis of a pseudomorphic high electron mobility transistors (pHEMT). The developed neural network model is used for designing a pHEMT power amplifier. The calculated S-parameters, gain and minimum noise figure from the artificial neural networks (ANN) model are the parameters used to design the low noise pHEMT power amplifier. The various gains so obtained from the S-parameters have been plotted with the frequency and it was found to yield a close fit to the simulated model. Neural network training has been done using Levenberg-Marqaurdt back propagation algorithm implemented in ANN toolbox of MATLAB software. All the results have been compared with the experimental data that showed a close agreement and validated our model. The calculated S-parameters, gain and minimum noise figure from the ANN model are the parameters used to design a stabilized and matched LNA.