Effect of Electric Field on Metallic SWCNT Interconnects for Nanoscale Technologies

The influence of an electric field on metallic single walled carbon nanotube(SWCNT) interconnects is studied. A voltage-dependent equivalent circuit model is presented for the impedance parameters of single-wall carbon nanotubes that capture various electron–phonon scattering mechanisms as a function of the electric field.To estimate the performance of SWCNT bundle interconnects, signal delay and power dissipation are calculated based on the field dependent model that results in an improvement in the delay and power estimation accuracy compared to the field-independent model. We find that the power delay product of a SWCNT bundle increases with the increase in electric field but decreases with technology scaling showing that at a low electric field, the SWCNT bundle is a potential reliable alternative interconnect for future high performance VLSI industry at scaled technologies.     

Circuit Modeling and Performance Analysis of GNR@SWCNT Bundle Interconnects

In this paper, the single-walled carbon nanotube(SWCNT) with graphene nanoribbon(GNR)inside, namely GNR@SWCNT, is proposed as alternative conductor material for the interconnect applications. The equivalent circuit model is established, and the circuit parameters extracted analytically. By virtue of the equivalent circuit model, the signal transmission performance of GNR@SWCNT bundle interconnect is evaluated and compared with its Cu and SWCNT counterparts. The optimal repeater insertions in glo...     

Scalable connection-based flow control scheme for application-specific network-on-chip

In this paper,a scalable connection-based flow control scheme is proposed for application-specific network-on-chip(NoC).The proposed scheme exploits two distinctive characteristics of NoC,namely traffic predictability and abundant wire resource,to achieve significant performance enhancements.First,the burst injection data are regulated into constant data streams and a connection-based method is used to ensure that all links are not overloaded at any time.Consequently,the number of packets in the network is decreased,leading to a reduced congestion probability and improved communication performance.Second,a simple architecture of the central controller is proposed to guarantee that the proposed scheme has small area overhead and is scalable.Simulation results show that compared with traditional switch-to-switch(STS) flow control scheme and pre-allocation based flow control schemes,the proposed scheme greatly increases the throughput and cuts down the average latency with reasonable area and energy overhead.     

A low-power DCO using inverter interlaced cascaded delay cell

This paper presents a low-power small-area digitally controlled oscillator(DCO) using an inverters interlaced cascaded delay cell(IICDC).It uses a coarse-fine architecture with binary-weighted delay stages for the delay range and resolution.The coarse-tuning stage of the DCO uses IICDC,which is power and area efficient with low phase noise,as compared with conventional delay cells.The ADPLL with a DCO is fabricated in the UMC 180-nm CMOS process with an active area of 0.071 mm2.The output frequency range is 140–600 MHz at the power supply of 1.8 V.The power consumption is 2.34 m W @ a 200 MHz output.     

Global Uniform Asymptotic Stability of Competitive Neural Networks with Different-Time Scales and Delay

The global uniform asymptotic stability of competitive neural networks with different time scales and delay is investigated. By the method of variation of parameters and the method of inequality analysis, the condition for global uniformly asymptotically stable are given. A strict Lyapunov function for the flow of a competitive neural system with different time scales and delay is presented. Based on the function, the global uniform asymptotic stability of the equilibrium point can be proved.     

含空位缺陷碳化硅纳米管的电子结构和光学性质

Based on first-principle calculations,the electronic structures and optical properties of a single-walled (7,0) SiC nanotube(SiCNT) with a carbon vacancy defect or a silicon vacancy defect are investigated.In the three silicon atoms around the carbon vacancy,two atoms form a stable bond and the other is a dangling bond.A similar structure is found in the nanotube with a silicon vacancy.A carbon vacancy results in a defect level near the top of the valence band,while a silicon vacancy leads to the formation of three defect levels in the band gap of the nanotube.Transitions between defect levels and energy levels near the bottom of the conduction band have a close relationship with the formation of the novel dielectric peaks in the lower energy range of the dielectric function.     

Interconnects for nanoscale MOSFET technology: a review

In this paper,a review of Cu/low-k,carbon nanotube(CNT),graphene nanoribbon(GNR)and optical based interconnect technologies has been done,Interconnect models,challenges and solutions have also been discussed.Of all the four technologies,CNT interconnects satisfy most of the challenges and they are most suited for nanometer scale technologies,despite some minor drawbacks.It is concluded that beyond 32nm technology,a paradigm shift in the interconnect material is required as Cu/low-k interconnects are approaching fundamental limits.     

A copper/polyimide Metal-base packaging technology

A unique substrate MCPM (Mitsubishi Copper Polyimide Metal-base) technology has been developed by applying our basic copper/polyimide technology.¹ This new substrate technology MCPM is suited for a high-density, multi-layer, multi-chip, high-power module/package, such as used for a computer. The new MCPM was processed using a copper metal base (110 × 110 mm), full copper system (all layers) with 50-μm fine lines. As for pad metallizations for the IC assembly, we evaluated both Ni/Au for chip and wire ICs and solder for TAB ICs. The total number of assembled ICs is 25. To improve the thermal dispersion, copper thermal vias are simultaneously formed by electro-plating. This thermal via is located between the IC chip and copper metal base, and promotes heat dispersion. We employed one large thermal via (4.5 mm^?) and four small vias (1.0 mm^?) for each IC pad. The effect of thermal vias and/or base metal is simulated by a computer analysis and compared with an alumina base substrate. The results show that the thermal vias are effective at lowering the temperature difference between the IC and base substrate, and also lowering the temperature rise of the IC chip. We also evaluated the substrate’s reliability by adhesion test, pressure cooker test, etc.     

Standard Analysis for Transfer Delay in CTCS-3

According to the standard for the GSM for railway (GSM-R) wireless systems in China train control system level 3 (CTCS-3),the control data transfer delay should be no larger than 500ms with greater than 99％ probability.Coverage of both non-redundant networks and intercross redundant networks and cases of single Mobile terminals (MTs) and redundant MTs on one train are considered,and the corresponding vehicle-ground communication models,delay models,and fault models are constructed.The simulation results confirm that the transfer delay can meet the standard requirements under all cases.In particular,the probability is greater than 99.996％ for redundant MTs and networks,and the standard of transfer delay in CTCS-3 will be improved inevitably.     

Mechanism of electromigration failure in submicron Cu interconnects

This paper reports on two different electromigration-failure mechanisms competing in Cu interconnects. Accelerated electromigration tests are conducted on identical single-level, 0.25-μm Cu interconnects with SiN or SiCN passivation. The results indicate that the failure mechanism can vary with the interface condition of the capping layer. The first failure mechanism, seen primarily in SiN-capped samples, is characterized by extensive interface damage, believed to be a result of failure led by interface electromigration. In this failure mode, damage initiates at the capping interface but gradually spreads along all interfaces of the Cu to form an isolated strand. The competing failure mechanism, found in SiCN-capped samples, is characterized by the formation and growth of a localized void without extensive interface damage. The absence of interface damage, in addition to the higher activation energy for failure, suggests that the failure occurs at a more localized inhomogeneity than the interface, such as grain boundaries. While the exact mechanism of how the capping layer suppresses one mechanism and promotes the other is unknown, this study reveals that the passivation-interface material and condition have a decisive role in determining the failure mechanism in Cu interconnects.     

Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects

Metallic carbon nanotubes (CNTs) have received much attention for their unique characteristics as a possible alternative to Cu interconnects in future ICs. Until this date, while almost all fabrication efforts have been directed toward multiwalled CNT (MWCNT) interconnects, there is a lack of MWCNT modeling work. This paper presents, for the first time, a detailed investigation of MWCNT-based interconnect performance. A compact equivalent circuit model of MWCNTs is presented for the first time, and the performance of MWCNT interconnects is evaluated and compared against traditional Cu interconnects, as well as Single-Walled CNT (SWCNT)-based interconnects, at different interconnect levels (local, intermediate, and global) for future technology nodes. It is shown that at the intermediate and global levels, MWCNT interconnects can achieve smaller signal delay than that of Cu interconnects, and the improvements become more significant with technology scaling and increasing wire lengths. At 1000- global or 500- intermediate level interconnects, the delay of MWCNT interconnects can reach as low as 15% of Cu interconnect delay. It is also shown that in order for SWCNT bundles to outperform MWCNT interconnects, dense and high metallic-fraction SWCNT bundles are necessary. On the other hand, since MWCNTs are easier to fabricate with less concern about the chirality and density control, they can be attractive for immediate use as horizontal wires in VLSI, including local, intermediate, and global level interconnects.     

Crosstalk Prediction of Single- and Double-Walled Carbon-Nanotube (SWCNT/DWCNT) Bundle Interconnects

The crosstalk effects in single- and double-walled carbon-nanotube (SWCNT and DWCNT) bundle-interconnect architectures are investigated in this paper. Some modified equivalent-circuit models are proposed for both SWCNT and DWCNT bundles, where capacitive couplings between adjacent bundles are incorporated. These circuit models are further used to predict the performance of SWCNT and DWCNT bundle interconnects in comparison with the Cu wire counterpart at all interconnect levels for advanced future technology generations. It is found that, compared with the SWCNT bundle, the DWCNT bundle interconnect can lead to a reduction of crosstalk-induced time delay, which will be more significant with increasing bundle length, while the peak voltage of the crosstalk-induced glitch in SWCNT and DWCNT bundle interconnects is in the same order as that of Cu wires. Due to the improvement in time delay, it is numerically confirmed that the DWCNT bundle interconnect will be more suitable for the next generation of interconnect technology as compared with the SWCNT bundle counterpart.      

Emerging interconnects: a state-of-the-art review and emerging solutions

Aluminium was a primary material for interconnection in integrated circuits (ICs) since their inception. Later, copper was introduced as interconnect material which has better metallic conductivity and resistance to electromigration. As the aggressive technology scaling continues, the copper resistivity increased because of size effects, which causes increase in delay, power dissipation and electromigration. The need to reduce the resistor-capacitor??????? delay, dynamic power utilisation and the crosstalk commotion is as of now the fundamental main impetus behind the presentation of new materials. The purpose of this paper is to do a survey of interconnect material used in IC from introduction of ICs to till date. This paper studies and reviews new materials available for interconnect application which are optical interconnects, carbon nanotube (CNT), graphene nanoribbons (GNRs) and silicon nanowires which are alternatives to copper. While doing a survey of interconnect material, it is found that multiwalled CNTs, multilayer GNR and mixed CNT bundles are promising candidates and are ultimate choice that can strongly address the problems faced by copper but on integration basis copper would last for coming years.     

Delay and crosstalk reliability issues in mixed MWCNT bundle interconnects

Multi-walled carbon nanotube (MWCNT) bundles have potentially provided attractive solution in nanoscale VLSI interconnects. In current fabrication process, it is not trivial to grow a densely packed bundle having MWCNTs with similar number of shells. A realistic nanotube bundle, in fact, is a mixed CNT bundle consisting of MWCNTs of different diameters. This research paper presents an analytical model of mixed CNT bundle wherein MWCNTs having different number of shells are densely packed. Two different types of MWCNT bundles are presented: (1) MB that contains MWCNTs with similar number of shells (i.e., uniform diameters) and (2) MMB wherein MWCNTs having different number of shells (i.e., non-uniform diameters) are mixed. Multi-conductor transmission line theory is used to present an equivalent single-conductor (ESC) model of different MB and MMB configurations. Using the ESC model, performance is analyzed to address the effect of propagation delay, crosstalk and power dissipation that explores the reliability of an interconnect wire. It is observed that using an MMB arrangement, the overall reduction in delay and crosstalk are 15.33% and 29.59%, respectively, compared to the MB for almost similar power dissipation.     

Modeling, Analysis, and Design of Graphene Nano-Ribbon Interconnects

Graphene nanoribbons (GNRs) are considered as a prospective interconnect material. A comprehensive conductance and delay analysis of GNR interconnects is presented in this paper. Using a simple tight-binding model and the linear response Landauer formula, the conductance model of GNR is derived. Several GNR structures are examined, and the conductance among them and other interconnect materials [e.g., copper (Cu), tungsten (W), and carbon nanotubes (CNTs)] is compared. The impact of different model parameters (i.e., bandgap, mean free path, Fermi level, and edge specularity) on the conductance is discussed. Both global and local GNR interconnect delays are analyzed using an RLC equivalent circuit model. Intercalation doping for multilayer GNRs is proposed, and it is shown that in order to match (or better) the performance of Cu or CNT bundles at either the global or local level, multiple zigzag-edged GNR layers along with proper intercalation doping must be used and near-specular nanoribbon edge should be achieved. However, intercalation-doped multilayer zigzag GNRs can have better performance than that of W, implying possible application as local interconnects in some cases. Thus, this paper identifies the on-chip interconnect domains where GNRs can be employed and provides valuable insights into the process technology development for GNR interconnects.      

Design and Performance Modeling for Single-Walled Carbon Nanotubes as Local, Semiglobal, and Global Interconnects in Gigascale Integrated Systems

Based on physical models, distributed circuit models are presented for single-walled carbon nanotubes (SWCNs) and SWCN bundles that are valid for all voltages and lengths. These models can be used for circuit simulations and compact modeling. It is demonstrated that by customizing SWCN interconnects at the local, semiglobal, and global levels, several major challenges facing gigascale integrated systems can potentially be addressed. For local interconnects, monolayer or multilayer SWCN interconnects can offer up to 50% reduction in capacitance and power dissipation with up to 20% improvement in latency if they are short enough (<20 mum). For semiglobal interconnects, either latency or power dissipation can be substantially improved if bundles of SWCNs are used. The improvements increase as the cross-sectional dimensions scale down. For global interconnects, bandwidth density can be improved by 40% if there is at least one metallic SWCN per 3-nm² cross-sectional area     

Evaluating the impact of resistance in carbon nanotube bundles for VLSI interconnect using diameter-dependent modeling techniques

Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper interconnects. This paper discusses the modeling of nanotube bundle resistance for on-chip interconnect applications. Based on recent experimental results, the authors model the impact of nanotube diameter on contact and ohmic resistance, which has been largely ignored in previous bundle models. The results indicate that neglecting the diameter-dependent nature of ohmic and contact resistances can produce significant errors. Using the resistance model, it is shown that SWCNT bundles can provide up to one order of magnitude reduction in resistance when compared with traditional copper interconnects depending on bundle geometry and individual nanotube diameter. Furthermore, for local interconnect applications, an optimum nanotube diameter exists to minimize the resistance of the carbon nanotube bundle.     

Low-power and high-performance techniques in global interconnect signaling

In this article, two accurate and efficient approaches are proposed to optimize the power and delay of global interconnects in VLSI ICs. We modify the conventional buffer insertion and low swing methods for delay and power optimization of various lengths of the global interconnects. As such, we address non-equidistance buffer insertion (NEBI) and current-mode driver and receiver (CMDR) techniques along with our smart optimization procedure. It is shown that the optimized low swing CMDR technique is efficient for global interconnects of the length equal or longer than 5 mm, and the improved buffer insertion technique, NEBI, is a perfect choice for the short global interconnects. Additionally, a random search algorithm known as simulated annealing (SA), improved by an intelligent method using a piecewise linear and exponential cost function, is employed for optimization of the power and delay. To this end, we have implemented a smart CAD tool that works interactively with HSPICE to achieve accurate and reliable design results. For verification purposes, several circuits are designed and simulated in 0.25, 0.18, and 0.13 μm CMOS technologies. The simulation results verify a significant reduction in the power and delay of global interconnects compared to other methods in the literature.     

Mixed carbon nanotube bundles for interconnect applications

The increasing resistivity of copper with scaling and demands for higher current density are the driving forces behind the ongoing investigation for new wiring solutions for deep nanometer scale VLSI technologies. Metallic carbon nanotubes (CNTs) are promising candidates that can potentially address the challenges faced by copper, and thereby extend the lifetime of electrical interconnects. This article examines the state of the art in CNT applications with focus on CNT interconnect research. It is observed that individually, single-wall carbon nanotubes (SWCNTs) and multi-wall carbon nanotubes (MWCNTs) exhibit characteristics that can be better exploited when a combination of the two is used – in the form of a CNT bundle that plays a vital role in interconnect applications. The focus here is that the usage of a combination of SWCNT (at the centre area of the bundle) and MWCNT (on the outside) provides great performance boost with lower interaction and crosstalk between neighbouring CNT bundles. Simulation results show that the resistance, capacitance, and inductance of a CNT depend on the probability of metallic CNTs present in the bundle and the length of the nanotube. Because Cu is metallic, it indicates that using a higher number of metallic nanotubes in the bundle would aid the CNT bundle performance. In addition, using MWCNT on the outer periphery of the bundle and SWCNT in the centre of the bundle would be the ideal way to maximise the performance of the bundle. Based on the observations we provide an analysis of why a mixed CNT bundle would be highly suitable as interconnections.