BiLink: A high performance NoC router architecture using bi-directional link with double data rate

This paper presents a novel high performance Network-on-Chip (NoC) router architecture design using a bi-directional link with double data rate (BiLink). Ideally, it can provide as high as 2 times speed-up compared with the conventional NoC router. BiLink utilizes an extra link stage between routers and transmits two flits in one link per cycle using phase pipelining if both routers require to use the current link. To further increase the effective bandwidth, the direction of each link can be configured in every clock cycle to cater for different traffic loads from each side. Therefore, the data rate can be as high as 4 times compared with conventional NoC routers under uneven traffic. Centralized mode control scheme is implemented using a finite state machine (FSM) approach. Cycle-accurate simulations are carried out on both synthetic traffic patterns as well as real application benchmarks. Simulation results show that BiLink can provide as high as 90% and 250% speedup compared with conventional NoC routers for even and uneven traffic, respectively. 2X and 3X gains in throughput are obtained under even and uneven traffic, respectively, when compared with the conventional NoC router for the virtual channel flow control. The BiLink router architecture is synthesized using TSMC 65 nm process technology and it is shown that an area overhead of 28% over state-of-the-art bi-directional NoC is introduced while the critical path is about 9% higher than that of the conventional routers. Despite the overhead in critical path and power consumption, a 47.45% improvement of Energy-Delay-Product (EDP) is achieved by BiLink under high injection rate traffic.     

Connection-based scheduling for supporting real-time traffic in wireless mesh networks

Packet transmission scheduling for supporting real-time traffic in a WMN is difficult, and one of the main challenges is to coordinate temporal operations of the mesh access points (APs) in order to provide strict latency guarantee while efficiently utilizing the radio resources. In this paper a connection-based scheduling (CBS) scheme is proposed. Connections with more hops are given a higher priority, and connections with a lower priority can only use resources remaining from serving all higher priority ones. For each multihop connection, the scheduling minimizes latency between successive hops. A connection-based optimization problem is formulated with an objective to minimize the amount of required AP resources, subject to the latency requirement of the connections. Numerical results show that the proposed scheduling scheme achieves close-to-optimum performance at both the connection and packet levels.     

Wavelength assignment for locally twisted cube communication pattern on optical bus network-on-chip

Optical network-on-chip (NoC) is a new designing of Multi-Processor System-on-Chip (MPSoC). Global bus is the simplest logical topology of optical NoC. Static routing and wavelength assignment is one important communication mechanism of optical NoC. This paper addresses the routing and wavelength assignment (RWA) problem for locally twisted cube communication pattern on global bus optical NoC. For that purpose, a routing scheme, that is an embedding scheme, is proposed, and a wavelength assignment scheme under the embedding scheme is designed. The number of required wavelengths is shown to attain the minimum, guaranteeing the optimality of the proposed scheme.     

Applying CDMA Technique to Network-on-Chip

The issues of applying the code-division multiple access (CDMA) technique to an on-chip packet switched communication network are discussed in this paper. A packet switched network-on-chip (NoC) that applies the CDMA technique is realized in register-transfer level (RTL) using VHDL. The realized CDMA NoC supports the globally-asynchronous locally-synchronous (GALS) communication scheme by applying both synchronous and asynchronous designs. In a packet switched NoC, which applies a point-to-point connection scheme, e.g., a ring topology NoC, data transfer latency varies largely if the packets are transferred to different destinations or to the same destination through different routes in the network. The CDMA NoC can eliminate the data transfer latency variations by sharing the data communication media among multiple users concurrently. A six-node GALS CDMA on-chip network is modeled and simulated. The characteristics of the CDMA NoC are examined by comparing them with the characteristics of an on-chip bidirectional ring topology network. The simulation results reveal that the data transfer latency in the CDMA NoC is a constant value for a certain length of packet and is equivalent to the best case data transfer latency in the bidirectional ring network when data path width is set to 32 bits.     

基于云模型进化算法的硅通孔数量受约束的3D NoC测试规划研究

针对硅通孔(TSV)价格昂贵、占用芯片面积大等问题,该文采用基于云模型的进化算法对TSV数量受约束的3维片上网络(3D NoC)进行测试规划研究,以优化测试时间,并探讨TSV的分配对3D NoC测试的影响,进一步优化3D NoC在测试模式下的TSV数量。该方法将基于云模型的进化算法、小生境技术以及遗传算法的杂交技术结合起来,有效运用遗传、优胜劣汰以及保持群落的多样性等理念,以提高算法的寻优速度和寻优精度。研究结果表明,该算法既能有效避免陷入局部最优解,又能提高全局寻优能力和收敛速度,缩短了测试时间,并且优化了3D NoC的测试TSV数量,提高了TSV的利用率。     

基于遗传算法的NoC互连测试研究

针对互连测试难题的分析,提出一种基于遗传算法的NoC互连测试方案。该方案采用NoC重用测试机制的方法,在功耗限制条件下,选取合适的测试端口和最短测试路径,同时根据互连测试中实际存在的问题,对算法进行适当改进,建立基于遗传算法的NoC互连测试模型,旨在获取最优矢量集的同时,测试代价更小。当NoC的规模达到一定程度时,采用划分测试方法,缩短测试路径,降低测试时间,提高测试效率。以SoCIN结构电路为仿真平台,分别对不同规模的NoC进行实验仿真。实验结果表明,遗传算法能快速有效地收敛到最优解,在测试运行代数及测试生成时间上取得了良好的测试效果。     

优化NoC性能的存储和通信压缩

文中针对NoC体系结构,提出了两种数据压缩技术,被称为高速缓存压缩和网络接口控制(NIC)内的压缩.性能实测结果指示压缩能够使NoC设计在较低的网络延迟、较低的功耗和改进应用性能等方面获得优势.     

基于FPGA的NoC验证平台的构建

针对基于软件仿真片上网络NoC（Network on Chip）效率低的问题,提出基于FPGA的NoC验证平台构建方案。该平台集成可重用的流量产生器TG（Traffic Generation）,流量接收器TR（Traffic Receiver）以及NoC软件,用于对NoC原型系统进行功能验证和性能评估。实际设计一个多核NoC,并用该平台对其进行FPGA验证,结果表明该平台的验证速度比软件仿真提高16000倍以上,并能对多种不同结构、路由算法、流控策略的NoC进行功能验证和性能评估。     

面向能耗和延时的NoC映射方法

 随着对NoC平台研究的逐步深入,如何将规模庞大的应用合理地映射到NoC平台上成为亟待解决的问题之一.本文基于二维网格结构NoC平台,建立了旨在优化系统通信能耗和执行时间的统一目标函数.提出了通过优化链路负载分布间接优化延时的方法,避免了NoC等待延时精确建模的难题.并且采用蚁群算法实现了面向能耗和延时的NoC映射.调整参数λ,可以选择单一目标或者联合目标优化.本文还对映射结果进行了执行时间模拟.实验结果显示:与随机映射相比,单一目标优化在通信能耗和执行时间上分别能节省(30%~47%)和(20%~39%),而联合目标优化则能在能量支配的映射方案中进一步挖掘时间维度的潜力.     

一种自适应的混合型无线NoC拓扑结构

针对传统大规模片上网络（Network-on-Chip,NoC）远距离核间多跳通信所带来的高能耗与延时问题,提出了一种基于虚Torus的自适应的混合型无线NoC拓扑结构（VT-AWiNoC）．该结构通过引入链路拥塞测度作为感知参数,基于此采用热点无线链路自动探测与带宽动态分配机制,并设计实现发送器动态分配的控制电路模块,以达到根据不同的通信流量模型,于片内自适应地调整拓扑结构及链路带宽的目的．通过建立混合型无线NoC的延时与功耗评估模型,对该结构的无线NoC进行性能评估．实验结果表明,该自适应拓扑与其它混合型无线NoC相比,在随机流量模型下,网络平均延时降低了16．52～23．27％;在20％的热点流量模型下,包平均能耗节省了39．19％;以真实应用FFT作为基准测试,平均延时降低了17．20％～21．68％,并节省了23．49％的包平均能耗．该结构以较小的面积开销获得了更优的性能．     

Mapping and Scheduling for Circuit‐Switched Network‐on‐Chip Architecture

Network‐on‐chip (NoC) architecture provides a high‐performance communication infrastructure for system‐on‐chip designs. Circuit‐switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real‐time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6×6, 8×8, and 10×10 mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit‐switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.     

Bio-inspired fault tolerant network on chip

The integration of heterogeneous processing elements (PEs) or nodes in the System on Chip (SoC) has made the communication structure very complex. The bus based system between these components is not able to handle the communication requirements and, this has led to the idea of Network on Chip (NoC). The NoC addresses the communication requirement of different nodes on SoC. The physical sizes of devices in NoC are scaled down, including routers, processing elements and interconnects, giving rise to faults, system delay, and latency issues. Fault tolerant routing algorithms are used to recover from temporary faults while redundant resources (wires, routers) are required to overcome the permanent faults. These routing algorithms, however, still suffer from congestion problems, low bandwidth, and throughput utilization as well as lacking adaptivity and robustness. In this work, novel biologically inspired techniques were proposed for NoC using combined best effort (BE) and guaranteed throughput (GT) services. Moreover, the bio-inspired algorithms are compared and analyzed with each other using BE, GT and combined BE-GT services. The bio-inspired mechanisms of “synaptogenesis” and “sprouting” have been adopted in the proposed NoC algorithms and architecture. These techniques were implemented using the BE and GT services. With the help of these two bio-inspired techniques, the NoC becomes robust, fault tolerant and is able to efficiently utilize the throughput and bandwidth. The bio-inspired algorithms improved the accepted traffic (flit/cycle/node) by 38.99% compared to different techniques in the literature. The bio-inspired algorithm also improved the bandwidth and throughput utilization by 71.04% and 72.42% respectively compared to the XY and Odd-Even fault tolerant routing algorithms. Moreover, the bio-inspired algorithm had less end-to-end latency and interflit arrival time by 196.44% and 88.10% respectively compared to the literature techniques of XY and Odd-Even.     

Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths

Reducing the NoC power is critical for scaling up the number of nodes in future many-core systems. Most NoC designs adopt packet-switching to benefit from its high throughput and excellent scalability. These benefits, however, come at the price of the power consumption and latency overheads of routers. Circuit-switching, on the other hand, enjoys a significant reduction in power and latency of communication by directing data over pre-established circuits, but the relatively large circuit setup time and low resource utilization of this switching mechanism is often prohibitive. In this paper, we address one of the major problems of circuit-switching, i.e. the circuit setup time overhead, by an efficient and fast algorithm based on the time-division multiplexing (TDM) scheme. We then further improve the performance by reserving circuits for anticipated messages, and hence completely hide circuit setup time. To address the low resource utilization problem, we integrate the proposed circuit-switching into a packet switched NoC and use unused circuit resources to transfer packet-switched data. Evaluation results show considerable reduction in NoC power consumption and packet latency.     

Test Scheduling for Network-on-Chip Using XY-Direction Connected Subgraph Partition and Multiple Test Clocks

It is attractive to reuse the on-chip functional interconnects as test access mechanism (TAM) in network-on-chip (NoC) system testing. However, in the methodology of NoC-reuse as TAM, the influence factors in NoC testing significantly increased. To further reduce test time and show significant gains over other work, we propose XY-direction connected subgraph partition (XYCSP) approach to eliminate the path conflicts before testing, and concurrently determine the position of test access points. We then present a multiple test clock strategy to bridge the gap between the NoC channel bandwidth and the core test wrapper bandwidth. With the help of adaptive probability gate quantum-inspired evolutionary algorithm (APGQEA) strategy, which blends adaptive strategy and multi-nary oriented techniques, the proposed NoC test scheduling algorithm permits quick exploration and exploitation of the solution space. Moreover, power constraints are also taken into account. Experimental results for the ITC’02 benchmarks show that the proposed scheme can achieve shorter test time compared to prior works.     

Communication-aware VFI partitioning for GALS-based networks-on-chip

The voltage/frequency island (VFI) design paradigm is a practical architecture for energy-efficient networks-on-chip (NoC) systems. In VFI-based NoC systems, each island can be operated with different voltage and clock frequency and thus it is important to carefully partition processing elements (PEs) into islands based on their workloads and communications. In this paper, we propose an energy-efficient design scheme that optimizes energy consumption and hardware costs in VFI-based NoC systems. Since on-chip networks take up a substantial portion of system power budget in NoC-based systems, the proposed scheme uses communication-aware VFI partitioning and tile mapping/routing algorithms to minimize the inter-VFI communications. Experimental results show that the proposed design technique can reduce communication energy consumption by 32–51% over existing techniques and total energy consumption by 3–14%.     

片上网络的动态虚通道分配策略

针对片上网络（NoC）的传统的静态虚通道分配不能很好适应非平衡的业务负荷问题,本论文提出了NoC动态虚通道分配策略。在静态虚通道分配基础上,动态分配虚通道通过实时监测节点端口的包流量的方向,决定分配给该端口的虚通道数目。动态虚通道资源可以在所有端口间共享,并根据通信业务需求动态调度。在二维meshNoC上的仿真表明,动态虚通道分配策略不仅节约了存储器资源,而且对NoC传输延时有一定的改善。     

基于内建自测技术的Mesh结构NoC无虚通道容错路由算法

 在Zhang's算法绕行思想的基础上,提出了一种2D-Mesh结构片上网络无虚通道容错路由算法,用于解决多故障节点情况下片上网络的无虚通道容错路由问题.算法利用内建自测试机制获取故障区域的位置信息,通过优化绕行策略来均衡故障区域周围链路的负载并减少部分数据的绕行距离.针对8×8的2D-Mesh网络的仿真表明,与Chen's算法相比,在故障区域大小为2×2,网络时延为70 cycles的情况下,随着故障区域位置的变化所提算法可提高1.2%到4.8%的网络注入率.且随着故障区域面积的扩大,所提算法在减少通信时延,提高网络吞吐量方面的作用更为明显.     

Topology and analysis of an N-stage cascaded polymer eight-port microring optical router with 7N channel wavelengths

Eight-port optical routers are widely used in cluster-mesh photonic networks-on-chip(No C). By using 24 groups of cross-coupling two-ring resonators, a 1-stage 8-port polymer optical router is proposed, which can optically route 7 channel wavelength data streams along definite path in two-dimensional(2D) plane. Under the selected 7 channel wavelengths, the insertion losses along all routing paths are within 0.02-0.58 d B, the maximum crosstalk of all routing operations is less than-39 d B, and the device footprint size is about 0.79 mm2. Then, a universal novel structure and routing scheme of N-stage cascaded 8-port optical router are presented, which contains 7N channel wavelengths. Because of the good scalability in wavelength, this device shows potential application of wideband signal routing in optical No C.     

基于包-电路交换的片上网络回退转向路由算法

采用包-电路交换的片上路由器,链路的建立通过发送请求包完成,而数据的传输则采用电路形式。传统的路由算法已经不能很好地适应基于包-电路交换的片上网络(NoC)新特性。该文根据包-电路交换的NoC的特点,提出了一种新的路由算法回退转向(RT)路由算法,以改善NoC性能。实验结果表明,与动态XY路由算法相比,回退转向路由算法使得网络平均吞吐量和平均包延迟最大分别改善26.7%和11.6%。     

SRNoC: A novel high performance Shared-Resource routing scheme for Network-on-Chip

This paper proposes a novel Shared-Resource routing scheme, SRNoC, that not only enhances network transmission performance, but also provides a high efficient load-balance solution for NoC design. The proposed SRNoC scheme expands the NoC design space and provides a novel effective NoC framework. SRNoC scheme mainly consists of the topology and routing algorithm. The proposed topology of SRNoC is based on the Shared-Resource mechanism, in which the routers are divided into groups and each group of routers share a set of specified link resource. Because of the usage of Shared Resource mechanism, SRNoC could effectively distribute the workload uniformly onto the network so as to improve the utilization of the resource and alleviate the network congestion. The proposed routing algorithm is a minimal oblivious routing algorithm. It could improve average latency and saturation load owing to its flexibility and high efficiency. In order to evaluate the load-balance property of the network, we proposed a method to calculate the Φ which represents the characteristic value of load-balance. The smaller the Φ, the better the performance in load-balance. Simulation results show that the average latency and saturation load are dramatically improved by SRNoC both in synthetic traffic patterns and real application traffic trace with negligible hardware overhead. Under the same simulation condition, SRNoC could cut down the total network workload to 48.67% at least. Moreover, SRNoC reduces the value of Φ 45% at least compared with other routing algorithms, which means it achieves better load-balance feature.