基于工艺参数扰动的随机互连线时延分析

考虑工艺参数扰动对互连电路传输性能的影响,建立了基于工艺扰动的互连线随机模型.通过改进的去耦算法对随机互连线元进行去耦,结合随机伽辽金方法(SGM)和多项式混沌展开(PCE)进行互连分析,进而利用复逼近及二分法给出工艺参数扰动下互连时延的有限维表达式.仿真实验结果不仅与SPICE仿真吻合得较好,相较于SPICE蒙特卡洛仿真还具有更高的计算效率.     

基于工艺参数扰动的随机互连线时延分析

考虑工艺参数扰动对互连电路传输性能的影响,建立了基于工艺扰动的互连线随机模型.通过改进的去耦算法对随机互连线元进行去耦,结合随机伽辽金方法(SGM)和多项式混沌展开(PCE)进行互连分析,进而利用复逼近及二分法给出工艺参数扰动下互连时延的有限维表达式.仿真实验结果不仅与SPICE仿真吻合得较好,相较于SPICE蒙特卡洛仿真还具有更高的计算效率.     

超深亚微米高速互连的信号串扰研究

探讨了超深亚微米设计中的高速互连线串扰产生机制,提出了一种描述高速互连串扰的电容、电感耦合模型,通过频域变换方法对模型的有效性进行了理论分析。针对0.18μm工艺条件提出了该模型的测试结构,进行了流片和测量。实测结果表明,该模型能够较好地表征超深亚微米电路的高速互连串扰效应,能够定量计算片上互连线间的耦合串扰,给出不同工艺的互连线长度的优化值。     

串扰约束下超深亚微米顶层互连线性能的优化设计

优化顶层互连线性能已成为超深亚微米片上系统(SOC)设计的关键.本文提出了适用于多个工艺节点的串扰约束下顶层互连线性能的优化方法.该方法由基于分布RLC连线模型的延迟串扰解析公式所推得.通过HSPICE仿真验证,对当前主流工艺(90nm),此优化方法可令与芯片边长等长的顶层互连线(23.9mm)的延时减小到182ps,数据总线带宽达到1.43 GHz/ μ m,近邻连线峰值串扰电压控制在0.096V_dd左右.通过由本方法所确定的各工艺节点下的截面参数和性能指标,可合理预测未来超深亚微米工艺条件下顶层互连线优化设计的发展趋势.     

IC中多余物缺陷对信号串扰的定量研究

该文研究了铜互连线中的多余物缺陷对两根相邻的互连线间信号的串扰,提出了互连线之间的多余物缺陷和互连线之间的互容、互感模型,用于定量的计算缺陷对串扰的影响。提出了把缺陷部分单独看作一段RLC电路模型,通过提出的模型研究了不同互连线参数条件下的信号串扰,主要研究了铜互连线的远端串扰和近端串扰,论文最后提出了一些改进串扰的建议。实验结果证明该文提出的信号串扰模型可用于实际的电路设计中,能够对设计人员设计满足串扰要求的电路提供指导。     

随机工艺变化下互连线ABCD参数建模与仿真

集成电路的不断发展使得互连线的随机工艺变化问题已经成为影响集成电路设计与制造的重要因素。基于电报方程建立了工艺变化下互连线的分布参数随机模型,推导出互连线ABCD参数满足的随机微分方程组,并提出了基于蒙特卡洛法的互连线ABCD参数统计分析方法,通过对ABCD参数各参量系数的正态性进行偏度-峰度检验,给出了最差情况估计。实验结果表明所提出的互连线随机模型及统计分析方法可以对工艺变化下的互连线传输性能进行有效的评估。     

互连线间容性串扰对延迟的影响

集成电路的性能越来越受到互连线间寄生效应的影响,特别是耦合电容的容性串扰,容性串扰引起互连线跳变模式相关的延迟。文中从E lm ore de lay定义的角度推导了互连线受同时跳变的阶跃信号激励时开关因子的大小,分析了互连线受非同时跳变的阶跃信号激励时耦合电容对互连线延迟的影响,给出了不同激励时的受害线延迟计算方法。分析表明,开关因子为0和2不能描述耦合电容对受害线延迟影响的下上限。H sp ice模拟结果证明了分析计算的准确性。     

高速互连线间的串扰规律研究

信号完整性中的串扰问题是目前高速电路设计中的难点和重点问题.利用高速电路仿真软件HSPICE和MATLAB软件,对高速电路中的互连线串扰模型进行了仿真分析,总结了三种变化因素下互连线问的串扰规律,对部分串扰规律进行了探索性的研究.     

工艺变化下互连线建模与ABCD参数仿真

考虑互连线工艺变化的空间相关性,采用数值仿真及拟合方法,得到电气分布参数的近似表达式,建立了互连线分布参数随机模型;推导出互连线ABCD参数满足的随机微分方程组,并提出基于蒙特卡洛法的ABCD参数统计分析方法;最后,通过对ABCD参数各参量系数的正态性进行偏度-峰度检验,给出最差情况估计.实验结果表明,提出的互连线随机模型及统计分析方法可以对工艺变化下的互连线传输性能进行有效的评估.     

一种65nm CMOS互连线串扰分布式RLC解析模型

基于65nm CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了一种互连线耦合串扰分布式RLC解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下,提出了被干扰线远端的串扰数值表达式.基于65nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在2.50%内,能应用于纳米级SOC的计算机辅助设计.     

Crosstalk-affected delay analysis in nanometer technologies

This article presents a detailed analysis of the crosstalk-affected delay of coupled interconnects considering process variations. We utilise a distributed RC-π model of the interconnections to accurately model process variations. In particular, we perform a detailed investigation of various crosstalk scenarios and study the impact of different parameters on crosstalk delay. Although accounting for the effect of correlations among parameters of the neighbouring wire segments, statistical properties of the crosstalk-affected propagation delays are characterised and discussed. Monte Carlo-based simulations using Spice demonstrate the effectiveness of the proposed approach in accurately modeling the correlation-aware process variations and their impact on interconnect delay in the presence of crosstalk.     

Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects

We introduce a Nyquist stability analysis of coupled mixed CNT bundle (MCB) for sub-threshold interconnects. In this analysis, the dependence of relative stability of sub-threshold MCBs with specific and probabilistic distribution of CNTs, on the geometry and probability of metallic CNTs, has been obtained. Using the proposed ABCD model and Nyquist stability criterion for sub-threshold MCBs, we show that, by increasing the diameter of each individual CNT and the length of MCB, the sub-threshold MCB interconnect system becomes more stable, while a densely packed MCB reduces the relative stability. Moreover, the crosstalk impact results in the greater stability of sub-threshold MCB system in comparison to a single interconnect. The crosstalk delay of MCB and composite Cu-MWCNT interconnects is also compared at various lengths. This is, so far, the first instance that such an analysis has been presented for coupled sub-threshold MCB interconnects.     

Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing

Every new VLSI technology generation has resulted in interconnects increasingly limiting the performance, area, and power dissipation of new processors. Subsequently, it is necessary to devise efficient interconnect design techniques to reduce the impact of VLSI interconnects on overall system design. New optimizations of a wave-pipelined multiplexed (WPM) interconnect routing circuit are described in this paper. These WPM circuits can be used with current interconnect repeater circuits to further reduce interconnect delay, interconnect area, transistor area, and/or power dissipation. For example, new area constrained WPM circuit optimizations illustrate that the interconnect circuit power can be reduced by 26% or the interconnect performance can be improved by 74%. Moreover, in both these cases, because a significant number of repeaters are eliminated, the transistor area can reduce by 41% or 29%, respectively. Finally, the tolerance of WPM circuits to crosstalk noise, power supply noise, clock skew, and manufacturing variations is also presented. This study of tolerance levels defines the conditions under which the WPM circuit will function correctly, and it is shown in this paper for the first time that WPM circuits are robust enough to operate with variability that can be encountered in deep submicrometer technologies.     

LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects

For system-on-chips (SoC) using deep submicron (DSM) technologies, interconnects are becoming critical determinants for performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods propose inserting dedicated interconnect self-test structures in the SoC to generate vectors which have high crosstalk defect coverage. However, these methods may have a prohibitively high area overhead. To reduce this overhead, existing logic BIST structures like LFSRs could be reused to deliver interconnect tests. But, as shown by our experiments, use of LFSR tests achieve poor crosstalk defect coverage. Additionally, it has been shown that the power consumed during testing can potentially become a significant concern.In this paper, we present Logic-Interconnect BIST (LI-BIST), a comprehensive self-test solution for both the logic of the cores and the SoC interconnects. LI-BIST reuses existing logic BIST structures but generates high-quality tests for interconnect crosstalk defects, while minimizing the area overhead and interconnect power consumption. The application of the LI-BIST methodology on example SoCs indicates that LI-BIST is a viable, low-cost, yet comprehensive solution for testing SoCs.     

Minimization of delay and crosstalk in high-speed VLSIinterconnects

Design optimization of time responses of high-speed VLSI interconnects modeled by distributed coupled transmission line networks is presented. The problem of simultaneous minimization of crosstalk, delay and reflection is formulated into minimax optimization. Design variables include physical/geometrical parameters of the interconnects and parameters in terminating/matching networks. A recently published simulation and sensitivity analysis technique for multiconductor transmission lines is expanded to directly address the VLSI interconnect environment. The new approach permits efficient physical/geometrical oriented interconnect design using exact gradient based minimax optimization. Examples of interconnect optimization demonstrate significant reductions of crosstalk, delay, distortion and reflection at all vital connection ports. The technique developed is an important step towards optimal design of circuit interconnects for high-speed digital computers and communication systems     

Optimal Positions of Twists in Global On-Chip Differential Interconnects

Crosstalk limits the achievable data rate of global on-chip interconnects on large CMOS ICs. This is especially the case, if low-swing signaling is used to reduce power consumption. Differential interconnects provide a solution for most crosstalk and noise sources, but not for neighbor-to-neighbor crosstalk in a data bus. This neighbor-to-neighbor crosstalk can be reduced with twists in the differential interconnect pairs. To reduce via resistance and metal layer use, we use as few twists as possible by placing only one twist in every even interconnect pair and only two twists in every odd interconnect pair. Analysis shows that there are optimal positions for the twists, which depend on the termination impedances of the interconnects. Theory and measurements on a 10-mm-long bus in 0.13-mum CMOS show that only one twist at 50% of the even interconnect pairs, two twists at 30% and 70% of the odd interconnect pairs, and both a low-ohmic source and a low-ohmic load impedance are very effective in mitigating the crosstalk     

Characteristic analysis of coupled HTS interconnects withtwo-dimensional FDTD

In this work, the frequency-dependent RLGC parameters of high-speed coupled high T_c superconductor (HTS) interconnects are extracted with a two-dimensional (2-D) FDTD algorithm. The response signals of an HTS interconnect circuit and a normal Al interconnect circuit are simulated and compared, showing that not only the signal dispersion, delay, and magnitude decay of HTS interconnects are smaller than that of Al interconnects, the crosstalk of HTS interconnects is much smaller, too     

Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores

In deep-submicron technologies, long interconnects play an ever-important role in determining the performance and reliability of core-based system-on-chips (SoCs). Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive due to the need for high-speed testers. Built-in self-test, while eliminating the need for a high-speed tester, may lead to excessive test overhead as well as overly aggressive testing. To address this problem, we propose a new software-based self-test methodology for system-on-chips (SoC) based on embedded processors. It enables an on-chip embedded processor core to test for crosstalk in system-level interconnects by executing a self-test program in the normal operational mode of the SoC, thereby allowing at-speed testing of interconnect crosstalk defects, while eliminating the need for test overhead and the possibility of over-testing. We have demonstrated the feasibility of this method by applying it to test the interconnects of a processor-memory system. The defect coverage was evaluated using a system-level crosstalk defect simulation method.