多晶硅超薄沟道薄膜晶体管研制

提出了一种新结构的低温多晶硅薄膜晶体管 ( poly- Si TFT) .该 poly- Si TFT由一超薄的沟道区和厚的源漏区组成 .超薄沟道区可有效降低沟道内陷阱密度 ,而厚源漏区能保证良好的源漏接触和低的寄生电阻 .沟道区和源漏区通过一低掺杂的交叠区相连接 .该交叠区使得在较高偏置时 ,靠近漏端的沟道区电力线能充分发散 ,导致电场峰值显著降低 .模拟结果显示该TFT漏电场峰值仅是常规 TFT的一半 .实验结果表明该 TFT能获得好的电流饱和特性和高的击穿电压 .而且 ,与常规器件相比 ,该 TFT的通态电流增加了两倍 ,而最小关态电流减少了3.5倍 .     

Halo LDD结构多晶硅薄膜晶体管的模拟研究

提出了多晶硅薄膜晶体管的一种Halo LDD新结构,这种结构是在基于LDD结构的基础上,在沟道靠近源、漏端引入高掺杂的Halo区.并利用工艺和器件模拟软件对该Halo LDD P-Si TFT的电学特性进行了分析,并将其与常规结构、LDD结构和Halo结构进行了比较.发现Halo LDD结构的P-si TFT能有效地降低泄漏电流、抑制阈值电压漂移和Kink效应;减少因尺寸减小后所带来的一系列问题.     

分析TFT亮态漏电流影响因素的测试方法

对于薄膜晶体管液晶显示器来说,TFT的特性对产品的品质有很大的影响,而其亮态漏电流Ioff的影响尤为重要。为改善器件性能,需要深入分析TFT亮态漏电流的影响因素。本文在实验基础上提出一种测试方法,首先使用BM PR(Black Matrix Photo Resist)对TFT沟道的不同位置进行遮挡;再对遮挡样品进行TFT特性测试。进而能模拟出实际工作中的TFT亮态漏电流,可以更加简便有效地优化TFT下方的栅极金属线宽,同时降低亮态漏电流。最后制作了54.6cm(21.5in)改善样品,通过新测试方法分析,将栅极金属线加宽约1.5μm,改善后样品的亮态漏电流从14.08pA降至约9.50pA。所以,使用新的测试方法无需将样品制作到模组后再进行品质评价,简单有效并降低了产品制造成本。     

电子回旋共振等离子氢钝化的高性能多晶硅薄膜晶体管

利用激光再结晶多条结构多晶硅膜作为半导体,研制出电子回旋共振(ECR)等离子氢钝化的高性能薄膜晶体管(TFT)。这些多晶硅TFT具有n沟道增强型特性,如大的跨导、高的开关比和低至0.4伏的阈值电压。为了获得TFT的理想特性,用激光再结晶多晶硅的ECR等离子氢钝化能有效地降低多晶硅的陷阱密度和大幅度提高载流子迁移率。通过这种钝化,多晶硅晶界性能得以改善,增加了TFT的跨导(gm),减小了源、漏极之间的漏电流。显然,这些高性能的TFT能得到高达2.5×10~9的开关比和低至10_(-14)A数量级的漏电流。     

MIC薄膜多晶硅材料的动态镍吸除技术基本机理及其应用

首先阐述了MIC薄膜多晶硅材料动态镍吸杂技术的基本机理和主要工艺过程,然后以多晶硅薄膜晶体管(poly-Si TFT)为例研究了动态吸杂技术的应用.在研究金属诱导晶化多晶硅材料(MIC poly-Si)和以之为有源层的poly-Si TFT的过程中,发现在MIC多晶硅薄膜中含有部分残余的镍成份.而大部分存在于对撞晶界的残余镍成份会造成大量的缺陷,这将导致TFT器件性能乃至整个系统的稳定性和可靠性的降低.为了改善MIC薄膜及器件质量,我们采用磷硅玻璃(PSG)动态镍吸杂技术,有效地吸除镍,降低多晶硅中镍的残留量,改善对撞晶界的缺陷密度,降低用之制备TFT的漏电流.该技术工艺过程简单,处理成本低,适合于大批量的工业化生产,有望成为制备高稳定性微电子器件与电路系统的必需工艺技术.     

MIC薄膜多晶硅材料的动态镍吸除技术基本机理及其应用

首先阐述了MIC薄膜多晶硅材料动态镍吸杂技术的基本机理和主要工艺过程,然后以多晶硅薄膜晶体管(poly-Si TFT)为例研究了动态吸杂技术的应用.在研究金属诱导晶化多晶硅材料(MIC poly-Si)和以之为有源层的poly-Si TFT的过程中,发现在MIC多晶硅薄膜中含有部分残余的镍成份.而大部分存在于对撞晶界的残余镍成份会造成大量的缺陷,这将导致TFT器件性能乃至整个系统的稳定性和可靠性的降低.为了改善MIC薄膜及器件质量,我们采用磷硅玻璃(PSG)动态镍吸杂技术,有效地吸除镍,降低多晶硅中镍的残留量,改善对撞晶界的缺陷密度,降低用之制备TFT的漏电流.该技术工艺过程简单,处理成本低,适合于大批量的工业化生产,有望成为制备高稳定性微电子器件与电路系统的必需工艺技术.     

金属栅薄膜全耗尽器件研究

实验并研究了采用金属栅工艺的全耗尽SOI MOS器件.采用LDD结构,以减小热载流子效应,防止漏击穿;采用突起的源漏区,以增加源漏区的厚度,并减小源漏区的串联电阻,以增强器件的电流驱动能力,降低寄生电阻,减小静态功耗.研究并分析了硅膜厚度对阈值电压和阈值电压漂移的影响,以及对本征栅电容和静态功耗的影响.与采用常规工艺的器件相比,提高了输出驱动电流,改善了器件的亚阈值特性,特别是在沟道掺杂浓度比较低的情况下,能得到非常合适的阈值电压.     

考虑源漏隧穿的DG MOSFET弹道输运及其模拟

在经典弹道输运模型中引入源漏隧穿(S/D tunneling),采用WKB方法计算载流子源漏隧穿几率,对薄硅层(硅层厚度为1nm)DG(dual gate)MOSFETs的器件特性进行了模拟.模拟结果表明当沟道长度为10nm时,源漏隧穿电流在关态电流中占25%,在开态电流中占5%.随着沟道长度进一步减小,源漏隧穿比例进一步增大.因此,模拟必须包括源漏隧穿.     

a-Si:H TFT亚阈值区SPICE模型的研究

研究了将非晶硅薄膜晶体管（a-Si：H TFT）在电路模拟程序（SPICE）中使用的亚阈值区模型,将亚阈值区分为亚阈值前区和亚阈值后区并建立了模型,对比了不同模型下的模拟结果,发现亚阈值区的TFT特性依赖于材料性质,而且亚阈值前区和亚阈值后区的特性受栅源电压Vcs和漏源电压V DS的影响,呈指数变化。提出的新模型考虑了前界面态、后界面态、局域态、材料及制作工艺等因素,体现了该区域电流对漏源电压Vvs强烈的依赖关系。使用新模型对实验数据的拟合结果优于以往的模型,能够比较精确地模拟亚阈值区的特性,可用来预测a-Si：H TFT的性能．对TFT阵列的模拟设计具有重要价值。     

Poly—Si TFT理论模型的研究

建立了一个poly-Si TFT的物理模型，并在此基础上分析了poly-Si材料特性对poly-Si TFT器件特性的影响。该模型考虑了晶粒和晶粒间界的不同特性，对泊松方程做了两维模型一维处理，用热电子发射模型重新定义了有效迁移率，推导出了poly-Si TFT电流电压关系的解析式。     

Ultra-thin elevated channel poly-Si TFT technology forfully-integrated AMLCD system on glass

A novel low temperature poly-Si (LTPS) TFT technology called the ultra-thin elevated channel TFT (UT-ECTFT) technology is proposed. The devices fabricated using this technology have an ultra-thin channel region (300 Å) and a thick drain/source region (3000 Å). The ultra-thin channel region is connected to the heavily doped thick drain/source region through a lightly doped overlapped region. The ultra-thin channel region is used to obtain a low grain-boundary trap density in the channel, and the overlapped lightly doped region provides an effective way for electric field spreading at the drain, thereby reducing the electric field there significantly. With the low grain-boundary trap density and low drain electric field, excellent current saturation characteristics and high drain breakdown voltage are obtained in the UT-ECTFT. Moreover, this technology provides complementary LTPS TFT's with more than two times increase in on-current and 3.5 times reduction in off-current compared to conventional thick channel LTPS TFT's     

A novel ultrathin elevated channel low-temperature poly-Si TFT

A novel ultrathin elevated channel thin-film transistor (UT-ECTFT) made using low-temperature poly-Si is proposed. The structure has an ultrathin channel region (300 Å) and a thick drain/source region. The thin channel is connected to the heavily doped drain/source through a lightly doped overlapped region. The lightly doped overlapped region provides an effective way to spread out the electric field at the drain, thereby reducing significantly the lateral electric field there at high drain bias. Thus, the UT-ECTFT exhibits excellent current saturation characteristics even at high bias (V_ds=30 V, V_gs=20 V). Moreover, the UT-ECTFT has more than two times increase in on-state current and 3.5 times reduction in off-state current compared to conventional thick channel TFT's     

Effects of silicon layer properties on device reliability for0.1-μm SOI n-MOSFET design strategies

We employ an advanced simulation method to investigate the effects of silicon layer properties on hot-electron-induced reliability for two 0.1-μm SOI n-MOSFET design strategies. The simulation approach features a Monte Carlo device simulator in conjunction with commercially available process and device simulators. The two channel designs are: 1) a lightly-doped (10¹⁶ cm^-3) channel and 2) a heavily-doped (10¹⁸ cm^-3) channel. For each design, the silicon layer thicknesses (T_Si) of 30, 60, and 90 nm are considered. The devices are biased under low-voltage conditions where the drain voltage is considerably less than the Si/SiO₂ barrier height for electron injection. A comparative analysis of the Monte Carlo simulation results shows that an increase in T_Si results in decreasing hot electron injection into the back oxide in both device designs. However, electron injection into the front oxide exhibits opposite trends of increasing injection for the heavily-doped channel design and decreasing injection for the lightly-doped channel design. These important trends are attributed to highly two-dimensional electric field and current density distributions. Simulations also show that the lightly-doped channel design is about three times more reliable for thick silicon layers. However, as the silicon layer is thinned to 30 nm, the heavily-doped channel design becomes about 10% more reliable instead     

A new polysilicon CMOS self-aligned double-gate TFT technology

In this paper, a new polysilicon CMOS self-aligned double-gate thin-film transistor (SA-DG TFT) technology is proposed and experimentally demonstrated. The self-alignment between the top- and bottom-gate is realized by a backlight exposure technique. The structure has an ultrathin channel region (300 /spl Aring/) and a thick source/drain region. Experimental results show that this technology provides excellent current saturation due to a combination of the effective reduction in the drain field and the full depletion of the ultrathin channel. Moreover, for n-channel devices, the SA-DG TFT has a 4.2 times higher on-current (V/sub gs/=20V) as compared to the conventional single-gate TFT. Whereas for the p-channel devices, the SADG TFT has a 3.6 times higher on-current (V/sub gs/=-20V) compared to the conventional single-gate device.     

Kink-free polycrystalline silicon double-gate elevated-channelthin-film transistors

The authors report the characterization and analysis of a novel double-gate elevated-channel thin-film transistor (ECTFT) fabricated using polycrystalline silicon. The transistor has a thin channel and thick source/drain regions with a double-gate control. Using this structure, the kink effect in the I-V characteristics of a conventional TFT is completely eliminated, and leakage current at zero gate bias is reduced by over 15 times. The elimination of the kink effect and the significant reduction in leakage current are obtained due to the reduction in lateral electric field at the channel/drain junction region. Two-dimensional (2-D) device simulations are used to study the electric field reduction mechanism in the structure. Experimental results on the forward conduction and gate transfer characteristics of the structure are also presented     

Increased resistance in p-type poly-Si resistors by thermal annealreduction interface charge

The effect of thermal annealing on characteristics of p-type poly-Si thin-film resistors was investigated. A significant increase was observed as the source/drain anneal temperature or anneal time was increased. The increased resistance is due to a reduction in current component arising from field-enhanced current via grain-boundary trap states at the drain end of the resistor. The reduction is this field-enhanced current arises primarily from a reduction of positive charge density at the top and bottom oxide/poly-Si interfaces of the thin-film resistor (and thus a reduction in the magnitude of the drain electric field) with increased annealing temperature and time     

Implementation and characterization of self-aligned double-gate TFTwith thin channel and thick source/drain

In this paper, a self-aligned double-gate (SADG) TFT technology is proposed and experimentally demonstrated for the first time. The self-alignment between the top-gate and bottom-gate is achieved by a noncritical chemical-mechanical polishing (CMP) step. A thin channel and a thick source/drain region self-aligned to the two gates are realized in the proposed process. Simulation results indicate that the self-aligned thick source/drain region leads to a significant reduction in the lateral electric field arisen from the applied drain voltage. N-channel poly-Si TFTs are fabricated with a maximum processing temperature of 600°C. Metal-induced unilateral crystallization (MIUC) is used to enhance the grain size of the poly-Si film. The fabricated SADG TFT exhibits symmetrical bi-directional transfer characteristics when the polarity of source/drain is reversed. The on-current under double-gate operation is more than two times the sum of that under individual top-gate and bottom-gate control. High immunity to short channel effects and kink-free current-voltage (I-V) characteristics are also observed in the SADG TFTs     

A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior     

A new poly-Si thin-film transistor with poly-Si/a-Si double activelayer

A new poly-Si TFT employing a rather thick poly-Si (400 Å)/a-Si(4000 Å) double active layer is proposed and fabricated in order to improve the stability of poly-Si TFT without sacrificing the on/off current ratio. Due to the thick double layer the on-state drain current of the proposed TFT flows through a broad current path near the drain junction so that the current density in the drain depletion region where large electric field is applied is considerably reduced. Consequently, additional trap state generation attributed to large current flow and large electric field in poly-Si channel decreases and the electrical stability of the proposed device has been considerably improved