低功耗、高线性度的电流模可编程增益放大器

本文设计了一种电流模式下,带电流模直流失调消除（DCOC）电路的class-AB的可编程增益放大器。电路基于电流放大器,可以实现40dB的增益动态范围,增益步长为1dB。电流模可编程增益放大器由0.18-μm CMOS工艺实现,电路具有较宽的电流增益范围、较低的直流功耗和较小的芯片面积。放大器电路芯片面积为0.099μm2,在1.8V电压下静态电流为2.52mA。测试结果表明电路增益范围为10dB到50dB,增益误差为±0.40dB,OP1dB为11.80dBm到13.71dBm,3dB带宽为22.2MHz到34.7MHz。     

高精度可变增益放大器的研究与设计

为了实现可变增益放大器高精度及大动态范围的优势,基于GaAs 0.25μm pHEMT工艺,设计了一款工作在0.1～4.0 GHz并行控制的可变增益放大器。放大器由数控衰减器和射频放大器组成。数控衰减单元采用桥T型结构和电平转换电路来实现;正压控制衰减电路简化了电路结构,提高电路可靠性;改进型并联电容补偿衰减结构改善大衰减态高频衰减精度;射频放大器电路采用并联电阻负反馈的共源共栅（Cascode）结构,实现了高增益平坦度和大动态范围。测试结果显示,在工作频带内,可变增益放大器的增益可达20 dB以上、平坦度在1.5 dB以内,可变增益范围为0～31.5 dB、衰减步进0.5 dB,输出三阶交调点最高可达39 dBm,端口回波损耗均小于-15 dB。     

一种1.9 GHz高性能功率预放大器的设计

介绍了一个基于0.35μm CMOS 6层金属工艺,采用片外阻抗匹配网络的两级AB类功率预放大器。电路在3.3 V电源电压下工作,静态电流为18 mA。测得功率预放大器的功率增益为10 dB,最大有6 dBm输出功率到50Ω负载。采用片上线性化技术,功率预放大器在1.9 GHz频率获得了很好的线性度:输出三阶截点OIP3=9.4 dBm,输出1 dB压缩点OP1 dB=-0.6dBm。     

全光增益控制的增益平坦型高功率光纤放大器

采用两级放大结构,利用光纤环形镜(FLM)并结合两根光纤光栅(FBG)进行增益平坦和增益控制,搭建了全光增益控制的增益平坦型高功率光纤放大器,实验测试了放大器的输出性能。放大器最大输出功率为1.399 W。在1535~1547nm范围内,增益不平坦度为±0.75dB。研究了信道在小功率和大功率信号输入条件下,放大器的增益控制特性,当信道2的功率在-33.7dBm~-2.5dBm和-14.8dBm~16.4dBm范围内变化时,剩余信道1的增益漂移范围可以分别达到0.04dB和0.06dB。     

基于SiGe工艺的高增益射频功率放大器

基于0.13μm SiGe HBT工艺,设计应用于无线局域网(WLAN)802.11b/g频段范围内的高增益射频功率放大器.该功放工作在AB类,由三级放大电路级联构成,并带有温度补偿和线性化的偏置电路.仿真结果显示:功率增益高达30dB,1dB压缩点输出功率为24dBm,电路的S参数S11在1.5～4GHz大的频率范围内均小于-17dB,S21大于30dB,输出匹配S22小于-10dB,S12小于-90dB.最高效率可达42.7%,1dB压缩点效率为37%.     

应用于DVB-T调谐器的CMOS可变增益中频放大器设计

采用TSMC 0.18μm RF CMOS工艺设计了一种适用于DVB-T调谐器的可变增益中频放大器。该放大器以信号相加式单元为主体电路,采用三级级联结构,实现了对数增益随控制电压连续、近似线性地变化和51dB的增益动态范围。仿真结果表明,在1.8V电源电压下,电路工作电流为30mA,3dB带宽为2-156MHz。增益调节范围为7.4-58.4dB,噪声系数小于8.6dB,输出三阶互调点大于0.6dBm。     

一种指数增益控制型高线性CMOS中频可变增益放大器

采用跨导线性化技术设计了一种具有指数增益特性的高线性中频可变增益放大器.该放大器由电流调节型可变增益单元、宽范围指数电压转换电路及固定增益放大器构成.基于0.25μm CMOS工艺的测试结果表明,放大器实现了8～48dB的增益连续变化,差分输出1V峰峰值下的三阶互调失真小于-60dBc,最大增益处噪声系数为8.7dB,50Ω负载下三阶输出截点为14.2dBm.     

一种指数增益控制型高线性CMOS中频可变增益放大器

采用跨导线性化技术设计了一种具有指数增益特性的高线性中频可变增益放大器.该放大器由电流调节型可变增益单元、宽范围指数电压转换电路及固定增益放大器构成.基于0.25μm CMOS工艺的测试结果表明,放大器实现了8～48dB的增益连续变化,差分输出1V峰峰值下的三阶互调失真小于-60dBc,最大增益处噪声系数为8.7dB,50Ω负载下三阶输出截点为14.2dBm.     

一种高精度宽带可编程增益放大器设计

基于SMIC 180 nm混合信号CMOS工艺,1．8 V电源电压供电,设计了一种应用于射频前端芯片的高精度宽带全差分可编程增益放大器（PGA ）．该PGA采用四级级联结构,且带有直流失调校准电路和可驱动50Ω电阻负载的超级源随器．流片测试结果表明,该PGA性能良好,由六位数字控制字实现0～50 dB增益范围变化,1 dB步进,步长误差小于0．2 dB ,1 dB带宽大于75 M Hz ,3 dB带宽大于110 M Hz ,放大电路部分消耗9 mA电流,输出buffer电路部分消耗8 mA电流,芯片有效面积为518μm ×406μm ．     

0.18μm CMOS可编程增益放大器

介绍了一种基于0.18μm CMOS工艺,应用于5 GHz无线局域网(WLAN)的可编程增益放大器(PGA)。该PGA采用分级可选放大器的系统结构,核心电路由交叉耦合的共源共栅放大器和电流反馈放大器组成。为消除工艺角偏差对增益精度的影响,设计中加入了增益微调的机制。后仿真结果表明:PGA电压增益可在0 dB到41 dB之间以1 dB步长变化,双端输出的电压摆幅为1 Vp-p,并具有大于10 MHz的-3 dB带宽和小于21.1 mW的静态功耗。     

A programmable gain amplifier with a DC offset calibration loop for a directconversion WLAN transceiver

A high-linearity PGA(programmable gain amplifier) with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA(RXPGA) provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA(TXPGA) covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA (I and Q path) under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC(DC offset cancellation) circuit shows 10 kHz of HPCF(high pass cutoff frequency) and the DCOC settling time is less than 0.45μs.     

Noise Analysis and Optimization of Programmable Gain Amplifier with DC Offset Cancelation

The noise contribution of a DC offset cancelation (DCOC) circuit in a programmable gain amplifier (PGA) is studied for the first time in this paper. The analysis presented shows that the DCOC-induced noise may deteriorate the PGA’s noise performance significantly if we do not pay enough attention to it. For an analog DCOC (ADCOC), it is concluded that the PGA’s noise increases rapidly as the output DC offset decreases, thereby causing difficulties to achieve both low noise and low DC offset simultaneously. We propose an optimization technique that can effectively alleviate the noise issue by increasing the feedback amplifier’s gain and the resistor’s value simultaneously, while maintaining a reasonable DC gain. For a digital DCOC (DDCOC), the extra noise comes from the transistors of the current source (sink) bank. The transistors with a longer channel length are preferred for their lower thermal and flicker noise current. The proof-of-concept prototypes are designed in a 0.18-\(\upmu \)m CMOS process, and a 3-stage PGA with ADCOC is fabricated. The measurement results validate the analysis and simulation results well.     

一种用于射频接收机的模拟基带电路

设计了一种无线传感网射频接收机中的基带电路,包括滤波器和可变增益放大器(VGA)。滤波器采用5阶切比雪夫型有源RC结构,带宽可调,具有自动调谐功能,能适应制造工艺与环境条件的变化。VGA由2阶放大器与1阶缓冲器组成,每阶放大器拥有一个DCOC环路,用来抑制直流失调,减小增益瞬态变化的稳定时间。采用TSMC 130 nm CMOS工艺进行流片。测试结果表明,供电电压为1.3 V时,滤波器能够涵盖8种带宽。自动调谐模块的调谐范围为±20%,调谐精度为2%。接收机的IIP3为28 dBm,双边带噪声为3 dB。VGA的增益变化范围为-12~56 dB。当VGA的增益瞬态变化量为32 dB时,DCOC的稳定时间小于100 ns。     

应用于多模接收机的低功耗可编程增益放大器

针对多模接收机的应用,提出了引入一条闭环伪通路技术结构的可编程增益放大器,在保持一定的线性度及噪声性能的基础上,以较低的功耗实现较大的带宽.该电路增益步长为2 dB,增益变化范围1～39 dB.电路中内嵌了直流失调消除模块防止直流漂移引起的阻塞.芯片采用SMIC 0.13 μm 1P8M RF CMOS工艺实现.测试结...     

A 60-dB linear VGA with novel exponential gain approximation

A CMOS variable gain amplifier (VGA) that adopts a novel exponential gain approximation is presented.No additional exponential gain control circuit is required in the proposed VGA used in a direct conversion receiver.A wide gain control voltage from 0.4 to 1.8 V and a high linearity performance are achieved. The three-stage VGA with automatic gain control (AGC) and DC offset cancellation (DCOC) is fabricated in a 0.18-μm CMOS technology and shows a linear gain range of more than 58-dB with a linearity error less than ± 1 dB. The 3-dB bandwidth is over 8 MHz at all gain settings. The measured input-referred third intercept point (IIP3) of the proposed VGA varies from -18.1 to 13.5 dBm, and the measured noise figure varies from 27 to 65 dB at a frequency of 1 MHz. The dynamic range of the closed-loop AGC exceeds 56 dB, where the output signal-to-noise-and-distortion ratio (SNDR) reaches 20 dB. The whole circuit, occupying 0.3 mm2 of chip area, dissipates less than 3.7 mA from a 1.8-V supply.     

应用于60GHz无线收发机内的带宽大于3GHz的无电感CMOS可编译增益放大器

这篇文章呈现了一个应用于60GHz无线收发机内的带宽大于3GHz的无电感CMOS可编译增益放大器,使用了改进的带负电容抵消技术Cherry-hooper放大器作为增益单元,采用了新颖的电路技术来实现增益调节,该技术在宽带PGA的设计中具有普适性,并且可以大大简化宽带PGA的设计。PGA通过两级增益单元和一级输出BUFFER的级联获得了最大增益30dB和远宽于3GHz的带宽。该PGA集成进整个60GHz无线收发机里面并且用TSMC65nm的CMOS工艺获得实现。整个接收机前端的测试结果表明接收机前端获得了18dB的可变增益范围和>3GHz的带宽,这证明提出的PGA本身获得了18dB的可变增益范围并且带宽是远大于3GHz的。该PGA电源电压为1.2V,功耗为10.7mW,核心版图面积仅仅为0.025mm^2。     

一种带功率检测和自适应偏置的CDMA功率放大器

设计了一款包含功率检测和自适应线性化偏置电路的CDMA功率放大器,功率检测器能根据输入信号的大小来调整功率管的偏置点,大幅提升低功率输出时的效率,从而提升系统整体效率;自适应线性化偏置能有效抑制功率放大器的增益压缩和相位失真,改善其线性度.采用2 μm InGaP/GaAs HBT晶体管工艺成功流片,测试结果表明,与普...     

用于W-LAN的5.8GHz InGaP/GaAs HBT MMIC线性功率放大器

介绍了一种应用于W-LAN系统的5.8 GHz InGaP/GaAs HBT MMIC功率放大器。该功率放大器采用了自适应线性化偏置电路来改善线性度和效率,同时偏置电路中的温度补偿电路可以抑制直流工作点随温度的变化,采用RC稳定网络使放大器在较宽频带内具有绝对稳定性。在单独供电3.6 V电压情况下,功率放大器的增益为26 dB,1 dB压缩点处输出功率为26.4 dBm,功率附加效率(PAE)为25%。三阶交调系数(IMD3)在输出功率为26.4 dBm时为-19 dBc,输出功率为20 dBm时低于-38 dBc,在1 dB压缩点处偏移频率为20 MHz时邻道功率比(ACPR)值为-31 dBc。     

A novel zero dead zone PFD and efficient CP for PLL applications

This paper presents a high dynamic range programmable gain amplifier (PGA) with linear-in-dB and digital to analog converter (DAC) gain control using a BiCMOS process. The proposed PGA is composed of a folded Gilbert variable gain amplifier cell, a DC offset cancellation circuitry, two inductorless fixed gain amplifiers with bandwidth extension, a symmetrical exponential voltage generator, a novel buffer amplifier with active inductive peaking for testing purposes and a 10 bit R-2R DAC. The linear-in-dB and DAC gain control scheme facilitate the analog baseband gain tuning accuracy and stability, which also provides an efficient way for digital baseband automatic gain control. The PGA chip is fabricated using 0.13 μm SiGe BiCMOS technology. With a power consumption of 80 mA@1.2 V supply voltage, the fabricated circuit exhibits a tunable gain range of ? 30–27 dB (DAC linear gain step guaranteed), a 3 dB bandwidth of around 3.5 GHz and a gain resolution of better than 0.07 dB.     

一种低功耗高分辨率可编程增益放大器的设计

该文设计了一种用于零中频接收机的低功耗高分辨率可编程增益放大器。该放大器采用源级电阻负反馈结构,利用跨导增强技术提高了放大器的线性度,并加入补偿电容扩展了带宽,实现了低功耗设计。该可编程增益放大器采用0.25μmCMOS工艺,仿真结果表明,在0.5pF负载电容的情况下,放大器增益动态的范围是0～62dB,2.5V供电电压下最大功耗为2.2mW,增益分辨率达到0.25dB,带宽10MHz,0dB增益时输入三阶交调点为17.9dBm。