一种指数增益控制宽范围可变增益放大器

采用中芯国际(SMIC)0.18μm CMOS工艺设计了一种具有指数增益特性的的宽增益调节范围的可变增益放大器,该放大器由Gilbert单元、指数电压转换电路、直流消除电路及超级源级跟随器组成。经过Cadence仿真验证,该放大器可以实现-11.14dB~30.39dB的增益连续变化,其-3dB带宽为250MHz,控制电压与增益成dB线性关系。     

下截止频率1.3～244Hz可调带通VGA设计

采用电压控制的伪电阻结构,设计了一款具有超低频下截止频率调节功能的带通可变增益放大器(VGA),由于该结构具有可调节超大的等效电阻和反馈电容使VGA的下截止频率可以调节.提出了一种改进的甲乙类运算跨导放大器(OTA)结构,采用新颖的浮动偏置设计,在满足高压摆率的条件下,有效提高共源共栅结构的电压输出范围.将伪电阻用于OTA的共模反馈,克服了阻性共模检测结构负载效应的问题.该VGA电路采用TSMC 0.18 μm标准工艺设计和流片,测试结果表明,1.2V电源电压下,其下截止频率调节范围为1.3～ 244 Hz,增益为49.2,44.2,39.2 dB,带宽为3.4,3.9,4.4 kHz,消耗电流为3.9 μA,共模抑制比达75.2 dB.     

应用于DVB-T调谐器的CMOS可变增益中频放大器设计

采用TSMC 0.18μm RF CMOS工艺设计了一种适用于DVB-T调谐器的可变增益中频放大器。该放大器以信号相加式单元为主体电路,采用三级级联结构,实现了对数增益随控制电压连续、近似线性地变化和51dB的增益动态范围。仿真结果表明,在1.8V电源电压下,电路工作电流为30mA,3dB带宽为2-156MHz。增益调节范围为7.4-58.4dB,噪声系数小于8.6dB,输出三阶互调点大于0.6dBm。     

增益精确的可变增益放大器

可变增益放大器是GPS接收机中的一个关键模块,它与反馈环路组成的自动增益控制电路为模/数转换器(ADC)提供恒定的信号功率.模拟信号控制增益的VGA增益连续变化,但是线性度较差.这里采用电阻形式的负反馈的放大器来设计一个0～30 dB增益变化的中频可变增益放大器,VGA的增益精度并不取决于工艺、电压和温度等因素对电阻、MOS管开关的影响,增益误差在各个工艺角下都小于5%.基于0.18 μm CMOS工艺的测试结果表明,带内纹波小于0.1 dB,IIP3达到31 dBm@0 dB,功耗为3 mA,其中包括直流偏移消除模块和CMOS源极跟随缓冲电路.因此,该放大器适合在接收机模拟前端使用.     

飞兆半导体推出1200V／15A NPT-Trench IGBT

美国模拟器件公司ADI近日发布了一款具高增益和带宽的直流（DC）耦合可变增益放大器（VGA）——AD8336。AD8336支持-55℃～＋125℃扩展工业温度范围和±3V～±12V工业和仪器仪表应用采用的电压范围的VGA。AD8336VGA适合高电压和宽温度范围的应用，它在60dB的增益范围内提供100MHz的带宽。AD8336的输入端包含一个电压反馈的运算放大器。前置放大器的标称增益为4倍（12dB），如果降低带宽可以获得20倍（26dB）增益。     

一种用于射频接收机的模拟基带电路

设计了一种无线传感网射频接收机中的基带电路,包括滤波器和可变增益放大器(VGA)。滤波器采用5阶切比雪夫型有源RC结构,带宽可调,具有自动调谐功能,能适应制造工艺与环境条件的变化。VGA由2阶放大器与1阶缓冲器组成,每阶放大器拥有一个DCOC环路,用来抑制直流失调,减小增益瞬态变化的稳定时间。采用TSMC 130 nm CMOS工艺进行流片。测试结果表明,供电电压为1.3 V时,滤波器能够涵盖8种带宽。自动调谐模块的调谐范围为±20%,调谐精度为2%。接收机的IIP3为28 dBm,双边带噪声为3 dB。VGA的增益变化范围为-12~56 dB。当VGA的增益瞬态变化量为32 dB时,DCOC的稳定时间小于100 ns。     

新品发布

RF VGA提供增益和功率控制单片射频(RF)可变增益放大器或衰减器(VGA)能提供1MHz～3GHz宽频带具有以dB为单位呈线性60dB增益控制范围,集成了宽带放大器和衰减器,具有60dB动态增益和衰减范围(大约+20dB增益和-40dB衰减),22dBm输出功率水平(1dB压缩点),在1GHz频率和8dB噪声系数下具有+31dBm输出三阶截点。ADIhttp://www.analog.com具有超低抖动的时钟AD951x系列时钟分配芯片集成了低相位噪声的PLL频率合成器内核、可编程分频器和可调延迟单元电路。器件具有亚皮秒抖动的低相位噪声时钟输出,LVPECL时钟输出达800MHz,附加抖动小…     

一款适用于WCDMA标准的大动态范围SiGe HBT可变增益放大器设计

第三代移动通信标准WCDMA要求放大器增益可调,并且增益动态范围较大.根据这一要求给出了一种基于SiGe HBT具有高动态范围的可变增益放大器(VGA)设计.放大器为三级级联结构,第一级为输入缓冲级,第二级为增益控制级,最后为放大级.VGA的增益控制通过调整第二级的偏置实现.VGA在1.95 GHz频率下,在0～2.7 V增益控制电压变化下,具有44 dB增益变化范围,最大增益49 dB.在最大增益处最小噪声系数为2.584 dB,输入输出电压驻波比低于2,性能良好.     

一种具有温度补偿的宽带CMOS可变增益放大器

设计实现了一个具有温度补偿的宽带CMOS可变增益放大器,该可变增益放大器的核心电路由三级基于改进型Cherry-Hooper结构的可变增益单元级联而成,并通过一种温度系数增强的且可编程的偏置电路和增益控制电路对可变增益放大器的增益进行温度补偿。采用中芯国际0.13μm CMOS工艺流片,测试结果表明可变增益放大器的可变增益范围为-13～27dB,经过温度补偿后,在相同增益控制电压下其增益在0～75°C温度范围内的变化范围不超过3dB。可变增益放大器的3dB带宽为0.8～3GHz,输入1dB压缩点为-50～-21dBm,在1.2V电压下,功耗为21.6mW。     

一种带有外部噪声识别功能的AGC电路的设计

基于红外遥控接收芯片中自动增益控制电路的功能需求及其应用环境,设计了一种能够有效抑制外部环境光干扰、线性度高的自动增益控制电路。该电路在传统自动增益控制电路的设计理念基础上引入外部噪声识别功能,设计的核心子电路包括具有线性增益特性的可变增益放大器、比较器以及利用空闲时间识别外部噪声的信号检测与增益控制电路。电路基于0.25μm标准CMOS工艺设计,使用Hspice软件进行仿真验证。仿真结果表明:电源电压为3~5 V,温度为0~85℃时,可变增益放大器的可控增益范围至少可达-69.5~27.6 dB,且至少具有42 dB的线性增益控制范围。     

A ± 0.75-V Compact CMOS Class-AB Current-Mode Exponential Variable Gain Amplifier

In this brief, a novel class-AB implementation of a current-mode exponential variable gain amplifier (VGA) is presented. The VGA is based on a novel current amplifier circuit implemented by multicoupled MOS translinear loops operating in strong inversion and saturation. The gain is conveniently configured for performing a pseudo-exponential approximation leading to a very compact design since an extra multiplier is not needed. Moreover the VGA can operate with very low voltage and power efficiency. Measurement results from a fabricated prototype in a 0.5-mum n-well CMOS technology reveal gain control up to 12 dB with errors less than plusmn0.5 dB and power consumption of 375 muW for a supply voltage of plusmn0.75 V.     

A 60-dB linear VGA with novel exponential gain approximation

A CMOS variable gain amplifier (VGA) that adopts a novel exponential gain approximation is presented.No additional exponential gain control circuit is required in the proposed VGA used in a direct conversion receiver.A wide gain control voltage from 0.4 to 1.8 V and a high linearity performance are achieved. The three-stage VGA with automatic gain control (AGC) and DC offset cancellation (DCOC) is fabricated in a 0.18-μm CMOS technology and shows a linear gain range of more than 58-dB with a linearity error less than ± 1 dB. The 3-dB bandwidth is over 8 MHz at all gain settings. The measured input-referred third intercept point (IIP3) of the proposed VGA varies from -18.1 to 13.5 dBm, and the measured noise figure varies from 27 to 65 dB at a frequency of 1 MHz. The dynamic range of the closed-loop AGC exceeds 56 dB, where the output signal-to-noise-and-distortion ratio (SNDR) reaches 20 dB. The whole circuit, occupying 0.3 mm2 of chip area, dissipates less than 3.7 mA from a 1.8-V supply.     

A 95-dB linear low-power variable gain amplifier

An all-CMOS variable gain amplifier (VGA) that adopts a new approximated exponential equation is presented. The proposed VGA is characterized by a wide range of gain variation, temperature-independence gain characteristic, low-power consumption, small chip size, and controllable dynamic gain range. The two-stage VGA is fabricated in 0.18-/spl mu/m CMOS technology and shows the maximum gain variation of more than 95 dB and a 90-dB linear range with linearity error of less than /spl plusmn/ 1 dB. The range of gain variation can be controlled from 68 to 95 dB. The P1dB varies from - 48 to - 17 dBm, and the 3-dB bandwidth is from 32 MHz (at maximum gain of 43 dB) to 1.05 GHz (at minimum gain of - 52 dB). The VGA dissipates less than 3.6 mA from 1.8-V supply while occupying 0.4 mm/sup 2/ of chip area excluding bondpads.     

Wide dynamic range variable-gain amplifier based on new approximated exponential equation

A new approximated exponential equation is proposed, which offers a wide decibel linear range for use in many applications such as exponential converters, log-domain filters, variable gain amplifiers (VGAs), automatic gain control amplifiers, etc. The proposed equation is implemented into a circuit as a two-stage VGA, which is fabricated in 0.18 mum CMOS technology and offers a gain range of 90 dB (-54-36 dB) and about 82 dB with linearity error of less than plusmn1 dB. The 3 dB bandwidth is 50 MHz at a maximum gain of 36 dB and P1 dB is from -40 to -17 dBm. The power dissipation is 3.7 mA from a 1.8 V supply. The chip, excluding bond pads, occupies 0.34 mm²     

A high-performance low-power CMOS AGC for GPS application

A wide tuning range, low power CMOS automatic gain control (AGC) with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier (VGA), a comparator and a charge pump, and the dB-linear gain is controlled by the charge pump. The AGC was implemented in a 0.18 μm CMOS technology. The dynamic range of the VGA is more than 55 dB, the bandwidth is 30 MHz, and the gain error is lower than ±1.5 dB over the full temperature and gain ranges. It is designed for GPS application and is fed from a single 1.8 V power supply.The AGC power consumption is less than 5 mW, and the area of the AGC is 700 × 450 μm~2.     

具有温度补偿及dB线性增益控制的单级宽范围CMOS可变增益放大器

提出了一种新颖的宽范围CMOS可变增益放大器结构.利用可变跨导和新颖的可变输出电阻,基于单独可变增益级的放大器可提供80dB的宽范围调节.同时控制电路的设计完成了温度补偿及dB线性增益特性,实现在整个温度及增益调节范围内绝对增益误差小于±1.5dB.基于0.25μm CMOS工艺验证表明,放大器可提供64.5dB的增益变化范围,其中dB线性范围为55.6dB.输入1dB压缩点为-17.5到11.5dBm,3dB带宽为65MHz到860MHz,2.5V电源供电下功耗为16.5mW.     

A single-stage variable-gain amplifier with 70-dB dynamic range for CDMA2000 transmit applications

A variable-gain amplifier (VGA) circuit is presented with a gain range of more than 70 dB in a single stage. Vertical stacking of multipliers in a single-stage VGA results in a considerable saving of power, which is a prime requirement in cellular systems. The gain-in-dB is a linear function of the control voltage and has excellent stability over temperature. The amplifier is a part of a code-division multiple access cellular transmit integrated circuit, and provides good linearity and noise characteristics over a wide range of IF frequencies. The circuit is fabricated in a 30-GHz f/sub t/ BiCMOS technology and consumes 8 mA at 2.7 V.     

Wideband CMOS variable gain amplifier with decibel-linear gain control characteristic

This paper presents a wideband variable gain amplifier (VGA) featuring a decibel-linear gain control characteristic. The decibel-linear gain control function is realized using two VGA cells and a control signal converter. The bandwidth is extended using cascode architecture together with active inductive load. To achieve small parasitic and low area, direct current (DC) coupling is adopted in the circuit while a DC offset cancellation circuit (DCOC) is introduced to cancel the DC offset. Fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process, the chip occupies an area of 0.53 mm × 0.48 mm (including pads) and draws a total current of 9 mA from a 1.8 V supply. The measurement results show that the gain of the VGA varies from -40 dB to 18 dB while the control voltage varies from 0 to 1.8 V, resulting in a total gain control range of 58 dB. The 3 dB bandwidth of the VGA is larger than 260 MHz at maximum gain.