ESD circuit model based protection network optimisation for extended-voltage NMOS drivers

New snapback circuit models for drain extended MOS (DEMOS) and complementary DEMOS-SCR structures used for ESD protection in high-voltage tolerant applications have been developed. The models were experimentally validated in a standard 0.35 μm CMOS process which requires 20 V compatible structures. It is shown that the new ESD models provide accurate representation of the structure breakdown, turn-on behaviour into conductivity modulation mode and dV/dt triggering effect, both in static and ESD transient conditions. A major application of this model is for initial ESD optimisation of complex mixed voltage analog circuits.     

一种CMOS IC片上电源ESD保护电路

随着集成电路工艺的高速发展,特征尺寸越来越小,静电放电对CMOS器件可靠性的危害也日益增大,ESD保护电路设计已经成为IC设计中的一个重要部分.讨论了两种常见的CMOS集成电路电源系统ESD保护电路,分析了它们的电路结构、工作原理和存在的问题,进而提出了一种改进的电源动态侦测ESD保护电路.使用HSPICE仿真验证了该电路工作的正确性,并且在一款自主芯片中使用,ESD测试通过士3000 V.     

Design of SCR‐Based ESD Protection Circuit for 3.3 V I/O and 20 V Power Clamp

In this paper, MOS‐triggered silicon‐controlled rectifier (SCR)–based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR‐based ESD protection circuits with floating diffusion regions for inverter and light‐emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded‐gate NMOS (ggNMOS) in the MOS‐triggered SCR‐based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P‐well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the floating diffusion region. The trigger voltage was improved by the partial insertion of a P‐body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low‐ and high‐voltage applications were designed using 0.18 µm Bipolar‐CMOS‐DMOS technology, with 100 µm width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS‐6008).     

基于状态方程法的不同ESD电路对比分析

针对IEC 61000-4-2中规定的典型静电放电(electrostatic discharge, ESD)电流波形存在拟合多样性且不易通过具体电路实现这一问题, 采用求解电路状态方程组的方法对四种ESD模拟器电路进行了计算.得到了四种指数形式的ESD电流解析表达式, 绘制了相应的电流曲线, 分别讨论了四种ESD模拟器电路产生的ESD电流波形解析式的连续性和可导性, 并对不同电路产生的ESD电流波形与IEC 61000-4-2标准规定电流波形之间的差异进行了对比分析.结果表明不同ESD电路产生的电流波形的四个主要指标符合IEC 61000-4-2标准规定, 但由于电路的拓扑结构和元件参数不同, 求得的电流波形解析式的连续性和可导性存在差异, 因此在选择ESD模型时, 应根据实际的人体参数和放电枪参数确定合适的电路结构.该计算方法适用于求解集总参数电路, 为ESD电磁脉冲辐射场仿真计算提供了新的电流解析式.     

Comprehensive ESD protection for RF inputs

We demonstrate that narrow-band tuned circuits may be used for ESD protection of RF inputs, and a figure of merit for optimization of these circuits is presented. The performance of the ESD-protected RF circuit is dependent on the quality factor of the ESD device, and various protection devices are evaluated in this work. Record-breaking human body model (HBM) protection levels, exceeding 5 kV, have been achieved without significantly degrading the RF performance at 5 GHz. Broadband circuit protection is also addressed.     

Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process

As CMOS processes advanced, the integration of radio-frequency (RF) integrated circuits was increasing. In order to protect the fully-integrated RF transceiver from electrostatic discharge (ESD) damage, the transmit/receive (T/R) switch of transceiver frond-end should be carefully designed to bypass the ESD current. This work presented a technique of embedded ESD protection device to enhance the ESD capability of T/R switch. The embedded ESD protection devices of diodes and silicon-controlled rectifier (SCR) are generated between the transistors in T/R switch without using additional ESD protection device. The design procedure of RF circuits without ESD protection device can be simplified. The test circuits of 2.4-GHz transceiver frond-end with T/R switch, PA, and LNA have been integrated and implemented in nanoscale CMOS process to test their performances during RF operations and ESD stresses. The test results confirm that the embedded ESD protection devices can provide sufficient ESD protection capability and it is free from degrading circuit performances.     

ESD Protection Design With On-Chip ESD Bus and High-Voltage-Tolerant ESD Clamp Circuit for Mixed-Voltage I/O Buffers

Considering gate-oxide reliability, a new electrostatic discharge (ESD) protection scheme with an on-chip ESD bus (ESD_BUS) and a high-voltage-tolerant ESD clamp circuit for 1.2/2.5 V mixed-voltage I/O interfaces is proposed. The devices used in the high-voltage-tolerant ESD clamp circuit are all 1.2 V low-voltage N- and P-type MOS devices that can be safely operated under the 2.5-V bias conditions without suffering from the gate-oxide reliability issue. The four-mode (positive-to-V_SS, negative-to-V_SS, positive-to-V_DD, and negative-to-V_DD) ESD stresses on the mixed-voltage I/O pad and pin-to-pin ESD stresses can be effectively discharged by the proposed ESD protection scheme. The experimental results verified in a 0.13-mum CMOS process have confirmed that the proposed new ESD protection scheme has high human-body model (HBM) and machine-model (MM) ESD robustness with a fast turn-on speed. The proposed new ESD protection scheme, which is designed with only low- voltage devices, is an excellent and cost-efficient solution to protect mixed-voltage I/O interfaces.     

Modeling of high voltage devices for ESD event simulation in SPICE

An ESD (electro-static-discharge) compact modeling methodology using a macro-modeling approach is introduced in this work for high voltage Lateral Double-diffused MOS (LDMOS) devices and new high-voltage protection clamps. The distinct characteristics of high voltage devices during high current/fast transient events are modeled without introducing convergence problems in ESD simulations for complex high voltage mixed-signal applications. The LDMOS ESD model consists of a sub-circuit that is built on top of the standard high-voltage MOS model (MOS20). The high voltage clamps, consisting of thyristor-type devices, are modeled using advanced bipolar junction transistor models.     

Stacked PMOS clamps for high voltage power supply protection

Large p-channel MOS (PMOS) field-effect transistors (FETs) with multiple gates can be arranged to provide ESD protection to high voltage on-chip power supplies in submicron integrated circuits. These clamps divide the supply voltage among several gate oxides; the circuitry accompanying the large series FETs provides near-maximum gate drive during the ESD for high pulsed current. Layouts are densely packed because minimum dimensions can be used and because no contact is needed between the stacked gates. The designs for high voltage are extensions of the large PMOS FET ESD clamps and timed drive circuitry that are used to clamp ordinary on-chip power supply lines.     

Highly Robust AHHVSCR‐Based ESD Protection Circuit

In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR‐based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch‐up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit — (i) an AHHVSCR‐based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR‐based ESD protection circuit, and (iii) a standard HHVSCR‐based ESD protection circuit. A circuit having the proposed new structure is fabricated using 0.18 μm Bipolar‐CMOS–DMOS technology. The fabricated circuit is also evaluated using Transmission‐Line Pulse measurements to confirm its electrical characteristics, and human‐body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.     

System ESD robustness by co-design of on-chip and on-board protection measures

System-level ESD robustness is a crucial feature for any electronic system. However, a consistent design methodology including IC-level protection, on-board protection and physical design of the module is still missing. The idea of a simple correlation between IC-level and system-level ESD robustness levels is misleading. A thorough characterization of the high current behaviour of IO circuit and on-board protection elements provides the necessary data for a simulation based co-design of on-chip and on-board protection measures. The constraints for characterization and modelling are discussed and the various protection measures for improved system-level ESD robustness are presented. Applying this methodology allows the development of a cost optimized system-level ESD protection throughout the stages of a system design.     

Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test

On-chip power-rail electrostatic discharge (ESD) protection circuit designed with active ESD detection function is the key role to significantly improve ESD robustness of CMOS integrated circuits (ICs). Four power-rail ESD clamp circuits with different ESD-transient detection circuits were fabricated in a 0.18-$mu{hbox{m}}$ CMOS process and tested to compare their system-level ESD susceptibility, which are named as power-rail ESD clamp circuits with typical RC-based detection, PMOS feedback, NMOS+PMOS feedback, and cascaded PMOS feedback in this work. During the system-level ESD test, where the ICs in a system have been powered up, the feedback loop used in the power-rail ESD clamp circuits provides the lock function to keep the ESD-clamping NMOS in a “latch-on” state. The latch-on ESD-clamping NMOS, which is often drawn with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. A modified power-rail ESD clamp circuit is proposed to solve this problem. The proposed power-rail ESD clamp circuit can provide high enough chip-level ESD robustness, and without suffering the latchup-like failure during the system-level ESD test.      

Ladder-shaped network for ESD protection of millimetre-wave CMOS ICs

A compact ladder-shaped electrostatic discharge (ESD) protection circuit is presented for millimetre-wave integrated circuits (ICs) in CMOS technology. Multiple shorted shunt stubs form a ladder network together with series stubs as ESD protection that discharges current/voltage pulses caused by an ESD event, while at the same time the network is embedded as part of the matching circuit for a normal operation. A 60 GHz low-noise amplifier using a 90 nm CMOS process is demonstrated with the proposed ESD protection methodology that introduces less than 1 dB insertion loss. Owing to the ESD current distribution through multiple shorted stubs, the proposed methodology is useful to millimetre-wave ICs with advanced CMOS technology that suffers from higher sheet resistance of the metal layers.     

CMOS on-chip electrostatic discharge protection circuit using four-SCR structures with low ESD-trigger voltage

A robust CMOS on-chip ESD protection circuit is proposed, which consists of four parasitic lateral SCR devices with low ESD trigger voltages to protect NMOS and PMOS devices of the internal circuits against the ESD pulses with both positive and negative polarities with respect to either VDD or VSS(GND) nodes. For each ESD stress with positive or negative polarity, there is an efficient and direct shunt path generated by the SCR low-impedance latching state to quickly bypass the ESD current. Thus, this four-SCR ESD protection circuit can perform very efficient protection in a small layout area. Since there is no diffusion or polysilicon resistor in the proposed ESD protection circuit, the RC delay between each I/O pad and its internal circuits is very low and high-speed applications are feasible. The experimental results show that this four-SCR protection circuit can successfully perform very effective protection against ESD damage. Moreover, the proposed ESD protection circuit is fully process-compatible with n-well or p-well CMOS and BiCMOS technologies.     

Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of ESD protection designs for mixed-voltage I/O interfaces with only low-voltage thin-oxide CMOS transistors. Especially, the ESD protection designs for mixed-voltage I/O interfaces with ESD bus and high-voltage-tolerant power-rail ESD clamp circuits are presented and discussed.     

CMOS VLSI ESD保护电路设计技术

本文对CMOSVLSI芯片ESD失效现象及其ESD事件发生机理进行了分析,介绍了CMOSVLSIESD保护电路设计技术。使用具有大电流放电性能的MOS器件构成的ESD电路,以及采用周密的版图布局布线技术,可实现良好的ESD保护性能。     

利用键合线提高ESD保护电路射频性能的研究

提出了一种利用键合线提高ESD保护电路射频性能的新型片外ESD保护电路结构。该新型结构在不降低ESD保护电路抗静电能力前提下,提高了ESD保护电路射频性能。针对一款达林顿结构ESD保护电路,制作了现有ESD保护电路结构和新型ESD保护电路结构的测试板级电路,测试结果表明:两种ESD保护电路结构的抗静电能力均达到20 kV,现有ESD保护电路结构在0～4.3 GHz频段内衰减系数均小于1 dB,反射损耗系数均小于-10 dB,最高工作频率为4.3 GHz;新型ESD保护电路结构在0～5.6 GHz频段内衰减系数均小于1 dB,反射损耗系数均小于-10 dB,最高工作频率为5.6 GHz。     

一种新型低漏电ESD电源箝位电路

在到达纳米级工艺后,传统的静电放电防护(ESD)电源箝位电路的漏电对集成电路芯片的影响越来越严重。为降低漏电,设计了一种新型低漏电ESD电源箝位电路,该箝位电路通过2个最小尺寸的MOS管形成反馈来降低MOS电容两端的电压差。采用中芯国际40 nm CMOS工艺模型进行仿真,结果表明,在相同的条件下,该箝位电路的泄漏电流仅为32.59 nA,比传统箝位电路降低了2个数量级。在ESD脉冲下,该新型ESD箝位电路等效于传统电路,ESD器件有效开启。     

CMOS集成电路中电源和地之间的ESD保护电路设计

讨论了3种常用的CMOS集成电路电源和地之间的ESD保护电路,分别介绍了它们的电路结构以及设计考虑,并用Hspice对其中利用晶体管延时的电源和地的保护电路在ESD脉冲和正常工作两种情况下的工作进行了模拟验证。结论证明：在ESD脉冲下,该保护电路的导通时间为380ns;在正常工作时。该保护电路不会导通．因此这种利用晶体管延时的保护电路完全可以作为CMOS集成电路电源和地之间的ESD保护电路。     

Analysis of 65 nm technology grounded-gate NMOS for on-chip ESD protection applications

Because of its simple structure and snapback characteristics, the grounded-gate NMOS (GGNMOS) has been widely used as an electrostatic discharge (ESD) protection device. ESD performance of GGNMOS fabricated in the 65 nm CMOS process is investigated, and measurement results for the snapback behaviour, failure current It2, holding voltage, and trigger voltage of such advanced MOS devices are illustrated. The effects of four key GGNMOS parameters, channel length, finger number, drain-to-gate spacing and source-togate spacing on the ESD performance, are considered, and optimal MOS structures for robust ESD protection applications are suggested.