A review on RF ESD protection design

Radio frequency (RF) electrostatic discharge (ESD) protection design emerges as a new challenge to RF integrated circuits (IC) design, where the main problem is associated with the complex interactions between the ESD protection network and the core RFIC circuit being protected. This paper reviews recent development in RF ESD protection circuit design, including mis-triggering of RF ESD protection structures, ESD-induced parasitic effects on RFIC performance, RF ESD protection solutions, as well as characterization of RF ESD protection circuits.     

Decreasing-size distributed ESD protection scheme for broad-band RF circuits

The capacitive load, from the large electrostatic discharge (ESD) protection device for high ESD robustness, has an adverse effect on the performance of broad-band RF circuits due to impedance mismatch and bandwidth degradation. The conventional distributed ESD protection scheme using equal four-stage ESD protection can achieve a better impedance match, but degrade the ESD performance. A new distributed ESD protection structure is proposed to achieve both good ESD robustness and RF performance. The proposed ESD protection circuit is constructed by arranging ESD protection stages with decreasing device size, called as decreasing-size distributed electrostatic discharge (DS-DESD) protection scheme, which is beneficial to the ESD level. The new proposed DS-DESD protection scheme with a total capacitance of 200 fF from the ESD diodes has been successfully verified in a 0.25-mum CMOS process to sustain a human-body-model ESD level of greater than 8 kV     

CMOS射频集成电路ESD保护的挑战

随着集成电路(IC)T艺进入深亚微米水平,以及射频(Radi0.Frequency,RF)IC工作频率向数千兆赫兹频段迈进,片上防静电泄放(ESD)保护设计越来越成为RF IC设计的挑战.产生这一挑战的关键原因在于ESD保护电路和被保护的RF IC核电路之间存在着不可避免的复杂交互影响效应.本文讨论了RF ESD保护的研究和设计领域的最新动态,总结了所出现的新挑战、新的设计方法和最新的RF ESD保护解决方案.     

Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process

As CMOS processes advanced, the integration of radio-frequency (RF) integrated circuits was increasing. In order to protect the fully-integrated RF transceiver from electrostatic discharge (ESD) damage, the transmit/receive (T/R) switch of transceiver frond-end should be carefully designed to bypass the ESD current. This work presented a technique of embedded ESD protection device to enhance the ESD capability of T/R switch. The embedded ESD protection devices of diodes and silicon-controlled rectifier (SCR) are generated between the transistors in T/R switch without using additional ESD protection device. The design procedure of RF circuits without ESD protection device can be simplified. The test circuits of 2.4-GHz transceiver frond-end with T/R switch, PA, and LNA have been integrated and implemented in nanoscale CMOS process to test their performances during RF operations and ESD stresses. The test results confirm that the embedded ESD protection devices can provide sufficient ESD protection capability and it is free from degrading circuit performances.     

ESD–RF co-design methodology for the state of the art RF-CMOS blocks

This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.     

CMOS射频集成电路ESD保护的挑战

随着集成电路(IC)T艺进入深亚微米水平,以及射频(Radi0.Frequency,RF)IC工作频率向数千兆赫兹频段迈进,片上防静电泄放(ESD)保护设计越来越成为RF IC设计的挑战.产生这一挑战的关键原因在于ESD保护电路和被保护的RF IC核电路之间存在着不可避免的复杂交互影响效应.本文讨论了RF ESD保护的研究和设计领域的最新动态,总结了所出现的新挑战、新的设计方法和最新的RF ESD保护解决方案.     

Interconnect Macromodelling and Approximation of Matrix Exponent

Electrostatic discharge (ESD) protection circuit design for radio-frequency (RF) integrated circuits emerges as a new design challenge. Yet currently, RF ESD protection is still a problem in definition. This paper proposes a new and comprehensive ESD-circuit interaction theory to address the complex mutual influences between the ESD protection networks and the circuits being protected in both directions. Design examples demonstrating the relevant key factors, e.g., switching and accidental triggering of ESD protection networks, as well as ESD-induced parasitic capacitive, resistive, noise coupling and self-generated noise effects, are provided to justify the new theory. Evaluation techniques, including s-parameter, Q-factor and overall specification examination, are discussed. The solutions to RF ESD protection are low-parasitic compact protection structures.     

CMOS集成电路中电源和地之间的ESD保护电路设计

讨论了3种常用的CMOS集成电路电源和地之间的ESD保护电路,分别介绍了它们的电路结构以及设计考虑,并用Hspice对其中利用晶体管延时的电源和地的保护电路在ESD脉冲和正常工作两种情况下的工作进行了模拟验证。结论证明：在ESD脉冲下,该保护电路的导通时间为380ns;在正常工作时。该保护电路不会导通．因此这种利用晶体管延时的保护电路完全可以作为CMOS集成电路电源和地之间的ESD保护电路。     

ESD protection design for CMOS RF integrated circuits using polysilicon diodes

ESD protection design for CMOS RF integrated circuits is proposed in this paper by using the stacked polysilicon diodes as the input ESD protection devices to reduce the total input capacitance and to avoid the noise coupling from the common substrate. The ESD level of the stacked polysilicon diodes on the I/O pad is restored by using the turn-on efficient power-rail ESD clamp circuit, which is constructed by substrate-triggered technique. This polysilicon diode is fully process compatible to general sub-quarter-micron CMOS processes.     

A 0.8-dB NF ESD-Protected 9-mW CMOS LNA operating at 1.23 GHz [forGPS receiver]

In recent years, much research has been carried out on the possibility of using pure CMOS, rather than bipolar or BiCMOS technologies, for radio-frequency (RF) applications. An example of such an application is the Global Positioning System (GPS). One of the important bottlenecks to make the transition to pure CMOS is the immunity of the circuits against electrostatic discharge (ESD). This paper shows that it is possible to design a low-noise amplifier (LNA) with very good RF performance and sufficient ESD immunity by carefully co-designing both the LNA and ESD protection. This is demonstrated with a 0.8-dB noise figure LNA with an ESD protection of -1.4-0.6 kV human body model (HBM) with a power consumption of 9 mW. The circuit was designed as a standalone LNA for a 1.2276-GHz GPS receiver. It is implemented in a standard 0.25-μm 4M1P CMOS process     

Analysis and design of distributed ESD protection circuits for high-speed mixed-signal and RF ICs

Electrostatic discharge (ESD) protection devices can have an adverse effect on the performance of high-speed mixed-signal and RF circuits. This paper presents quantitative methodologies to analyze the performance degradation of these circuits due to ESD protection. A detailed S-parameter-based analysis of these high-frequency systems illustrates the utility of the distributed ESD protection scheme and the impact of the parasitics associated with the protection devices. It is shown that a four-stage distributed ESD protection can be beneficial for frequencies up to 10 GHz. In addition, two generalized design optimization methodologies incorporating coplanar waveguides are developed for the distributed structure to achieve a better impedance match over a broad frequency range (0-10 GHz). By using this optimized design, an ESD device with a parasitic capacitance of 200 fF attenuates the RF signal power by only 0.27 dB at 10 GHz. Furthermore, termination schemes are proposed to allow this analysis to be applicable to high-speed digital and mixed-signal systems.     

ESD protection design considerations for InGaP/GaAs HBT RF power amplifiers

In order to design a robust electrostatic discharge (ESD) protected RF amplifier in InGaP/GaAs HBTs, a comprehensive assessment of device vulnerability to ESD events in both active transistors and passive components of the HBT technology is presented in this paper. The results include not only the intrinsic HBT's ESD robustness performance, but also its dependence on device layout, ballast resistor, and process. Acknowledging the ESD constraints imposed on InGaP/GaAs HBT technology, a 5.4-6.0-GHz power amplifier (PA) with a compact 2000 V/sub ESD/ (human body model) on-chip ESD protection circuit that has a low loading capacitance of less than 0.1 pF and that does not degrade RF and output power performance is developed for wireless local area network application. A diode triggered Darlington pair is implemented as the ESD protection circuit instead of the traditional diode string. Its operation principle, ESD protection performance, and PA performance are also illustrated in this paper.     

利用键合线提高ESD保护电路射频性能的研究

提出了一种利用键合线提高ESD保护电路射频性能的新型片外ESD保护电路结构。该新型结构在不降低ESD保护电路抗静电能力前提下,提高了ESD保护电路射频性能。针对一款达林顿结构ESD保护电路,制作了现有ESD保护电路结构和新型ESD保护电路结构的测试板级电路,测试结果表明:两种ESD保护电路结构的抗静电能力均达到20 kV,现有ESD保护电路结构在0～4.3 GHz频段内衰减系数均小于1 dB,反射损耗系数均小于-10 dB,最高工作频率为4.3 GHz;新型ESD保护电路结构在0～5.6 GHz频段内衰减系数均小于1 dB,反射损耗系数均小于-10 dB,最高工作频率为5.6 GHz。     

RF ESD protection strategies: Codesign vs. low-C protection

The present work is focussed on the trade-off between conventional RF ESD protection concepts optimized in terms of capacitive load and the frequently discussed RF ESD codesign idea with ESD protection skilfully integrated into RF circuit design. A narrow and a broadband RF test circuit were developed to put the benchmark on a firm basis. RF and ESD experiments are discussed, showing where the higher effort for the codesign approach starts to pay off.     

Built-in ESD Protection for RFID Tag ICs

The built-in Electro-Static discharge (ESD) protection circuits for Radio frequency identification (RFID) tag ICs are proposed.The ESD protection function is built into the rectifier and amplitude limiter.The rectifier and limiter are connected directly to the RF interface,and some transistors can discharge the larger current.These transistors can be used to build ESD protection circuits,through the redesign and optimization.The built-in ESD protection circuits can improve the ESD protection level and reduce the layout area.The circuits have been fabricated in 0.18μm CMOS process.The test results show that the built-in ESD protection circuits work well under 4kV ESD pressure and save as much as 72％ of the layout area compare with foundry standard ESD protection cells.     

A Fully Integrated 7.3 kV HBM ESD-Protected Transformer-Based 4.5–6 GHz CMOS LNA

The increasing mask costs of modern scaled CMOS makes silicon area precious. Meanwhile, the lowering oxide thickness seriously toughens ESD protection of RF circuits, pushing towards area-demanding inductor-based ESD protection techniques. This paper presents a transformer-based ESD protection technique for inductor-based LNAs. With no area penalty, an ESD protection level of 4.5 kV HBM is achieved. Introducing two-stage protection increases the robustness up to 7.3 kV, maintaining excellent RF performance. Further it extends the TLP protection level from 3.2 to 5 A. A noise figure of 2.6 dB is achieved with a power gain of 14.8 dB, while consuming 6.5 mW. The technique serves as a solution for low-area highly protected LNAs in deep-submicron CMOS.      

Evaluation of RF electrostatic discharge (ESD) protection in 0.18-μm CMOS technology

Electrostatic discharge (ESD) protection design is challenging for RF integrated circuits (ICs) because of the trade-off between the ESD robustness and parasitic capacitance. ESD protection devices are fabricated using the 0.18-μm RF CMOS process and their RF ESD characteristics are investigated by the transmission line pulsing (TLP) tester. The results suggest that the silicon controlled rectifier (SCR) is superior to the diode and NMOS from the perspective of ESD robustness and parasitic, but the SCR nevertheless possesses a longer turn-on time.     

Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process

The configurable electrostatic discharge (ESD) protection cells have been implemented in a commercial 65-nm CMOS process for 60-GHz RF applications. The distributed ESD protection scheme was modified to be used in this work. With the consideration of parasitic capacitance from I/O pad, the ESD protection cells have reached the 50-Ω input/output matching to reduce the design complexity for RF circuit designer and to provide suitable ESD protection. Experimental results of these ESD protection cells have successfully verified the ESD robustness and the RF characteristics in the 60-GHz frequency band. These ESD protection cells can easily be used for ESD protection design in the 60-GHz RF applications, and accelerate the design cycle.     

基于STNMOS的混合电压I／O接口ESD保护

混合电压I／O接口的静电放电（electrostaticdischarge,ESD）保护设计是小线宽工艺中片上系统（SoC）设计的主要挑战之一。混合电压I／O接口的片上ESD保护既要避免栅氧可靠性问题,又要防止不期望的泄漏电流路径产生。这篇论文讨论了基于堆叠NMOS（Stacked—NMOS,STNMOS）的混合电压I／O接口的ESD保护设计构思和电路实现,通过不同ESD保护设计方案的比较,提出了一个最有效的保护方案。     

Design and Analysis for a 60-GHz Low-Noise Amplifier With RF ESD Protection

An RF electrostatic discharge (ESD) protection for millimeter-wave (MMW) regime applied to a 60-GHz low-noise amplifier (LNA) in mixed-signal and RF purpose 0.13-$mu{hbox{m}}$ CMOS technology is demonstrated in this paper. The measured results show that this chip achieves a small signal gain of 20.4 dB and a noise figure (NF) of 8.7 dB at 60 GHz with 65-mW dc power consumption. Without ESD protection, the LNA exhibits a gain of 20.2 dB and an NF of 7.2 dB at 60 GHz. This ESD protection using an impedance isolation method to minimize the RF performance degradation sustains 6.5-kV voltage level of the human body model on the diode and 1.5 kV on the core circuit, which is much higher than that without ESD protection ( $≪$350 V). To our knowledge, this is the first CMOS LNA with RF ESD protection in the MMW regime and has the highest operation frequency reported to date.