Modeling and simulation of hot-carrier-induced device degradationin MOS circuits

The physical models and an integrated simulation tool are presented for estimating the hot-carrier-induced degradation of nMOS transistor characteristics and circuit performance. The proposed reliability simulation tool incorporates an accurate one-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors. The hot-carrier-induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. The physical degradation model includes both fundamental device degradation mechanisms, i.e., charge trapping and interface trap generation. A repetitive simulation scheme has been adopted to ensure accurate prediction of the circuit-level degradation process under dynamic operating conditions     

PMOSFET's热载流子退化模拟及寿命评估的统一模型

对 PMOSFET's几种典型器件参数随应力时间的退化规律进行了深入研究 ,给出了一个新的器件退化监控量 ,并建立了不同器件参数退化的统一模型 .模拟结果和测量结果的比较表明 ,新的退化模型具有较高的准确性和较宽的适用范围 .新的退化模型不但可以用于器件参数退化量的模拟 ,也可以用于器件寿命评估     

Simulation of hot-carrier induced MOS circuit degradation for VLSIreliability analysis

A new integrated simulation tool is presented for estimating the hot-carrier induced degradation of nMOS transistor characteristics and circuit performance. This reliability simulation tool incorporates: (1) an accurate 1-dimensional MOSFET model for representing the electrical behavior of locally damaged transistors; and (2) physical models for both fundamental device-degradation mechanisms (charge trapping and interface trap generation). Hot-carrier induced oxide damage can be specified by only a few parameters, avoiding extensive parameter extractions for the characterization of device damage. A repetitive simulation scheme ensures accurate prediction of the circuit-level degradation process under dynamic operating conditions. The evolution of hot-carrier related damage in each device is automatically simulated at predetermined time intervals, instead of extrapolating the long-term degradation using only the initial simulation results. Thus, the gradual variation of dynamic stress conditions is accounted for during the long-term damage estimates     

通过直接栅电流测量研究PMOSFET's热载流子损伤

通过直接栅电流测量方法研究了热载流子退化和高栅压退火过程中PMOSFET's热载流子损伤的生长规律.由此,给出了热载流子引起PMOSFET's器件参数退化的准确物理解释.并证明了直接栅电流测量是一种很好的研究器件损伤生长和器件参数退化的实验方法.     

Analysis of the gate current as a suitable indicator for FET degradation under nonlinear dynamic regime

Electron device degradation, although not directly accounted for, represents a key issue in microwave circuit design. This is especially true when the particular applications involved (e.g., satellite, military, consumer) do not allow or strongly discourage any kind of maintenance. As a matter of fact, in order to account for device degradation in circuit design, a suitable electron device model is needed which is able to predict the performance degradation as a function of the actual electrical regime involved in the device operation. Such a kind of model is not available in literature. In this paper, quantitative results are provided for device degradation indicators which correlate DC and RF stress experiments. These results can be considered an important step toward the definition of a nonlinear model accounting for device degradation.     

不同辐照剂量率下NPN晶体管的电流增益退化模型

电离辐照使NPN晶体管基极电流增加,导致电流增益退化。辐照感生的界面态使表面复合速率,感生的氧化物电荷改变基区表面势,导致表面复合率增加,这两者都引起基极电流增加;基于此,建立了电流增益退化模型。结合感生的界面态和氧化物电荷的产生机制,这个模型能够解释辐照导致的增益退化,以及增益退化的低剂量率增强效应。在Co60 源上进行了γ射线辐照试验,高剂量率为10 rad (Si)/,低剂量率为0.1 rad(Si)/s,总剂量为70krad(Si)。这个模型很好解释实验数据。     

A physical based model to predict performance degradation of FinFET accounting for interface state distribution effect due to hot carrier injection

A physical based model for predicting the performance degradation of the FinFET is developed accounting for the interface state distribution effect due to hot carrier injection (HCI). The non-uniform distribution of interface state along the FinFET channel is first extracted by a forward gated-diode method and then reproduced by an empirical model. From this, a physical-based device model, which accounts for the interface state distribution effect, is developed to predict the performance degradation of FinFET. The result shows that the developed model not only matches well with the experimental data of FinFET in all operation regions, but also predicts the asymmetric degradation of saturation drain current in forward and reverse operation mode. Finally, the impact of HCI to a 6-T SRAM cell is simulated using HSPICE.     

深亚微米HCI模型参数多目标全域提取方法

研究了一种建立在退化栅电流物理解析模型基础上的深亚微米pMOS器件HCI(hot carrier injection)退化模型. 提出了一种基于L-M (Levenberg-Marquardt）算法的多目标响应全域优化提取策略，并对可靠性模型参数进行优化提取. 分析了优化过程中由于参数灵敏度过低产生的问题并提出采用递归算法求解不同时刻栅电流注入电荷量的加速计算方法. 最后，给出了最优化参数提取的结果，并且将测量值与理论值进行了比较,得到很好的一致性.     

Relationship between MOSFET degradation and hot-electron-induced interface-state generation

Device degradation due to hot-electron injection in n-channel MOSFET's is mainly caused by mobility degradation and reduced mobile charges in the channel introduced by interface-state generation. With the use of simple gradual-channel approximation (GCA), a linear relationship is derived between the threshold shift, relative transconductance reduction, and the number of interface states generated. This model provides a link between the electrical characteristics of a degraded device and its physical damages and, therefore, is a vital tool in the study of hot-electron-induced device degradation mechanisms.     

Analytical Modeling of Output Conductance in Long-Channel Halo-Doped MOSFETs

In this paper, a detailed physical analysis and an analytical derivation of the degradation of the output resistance ($R_ out$) observed in relatively long-channel laterally nonuniformly doped devices with halo implants are presented. Two-dimensional device simulations were performed, and the simulations show that the channel can be split into two uniformly doped transistors in series for the purpose of analysis. The lower doped bulk transistor is on the source side, while the higher doped halo transistor is toward the drain end. Based on this two-transistor analysis, a simple$R_ out$degradation model is derived for implementation in a MOSFET compact model.     

Investigation of the degradation mechanisms of InP/InGaAs DHBT under bias stress conditions to achieve electrical aging model for circuit design

The reliability of InP/InGaAs DHBT under high collector current densities and low junction temperatures is analyzed and modeled. From the Gummel characteristics, we observe several types of device degradation, resulting from the long term changes of base and collector current in both lower and higher base–emitter voltage ranges which impacts the reduction of DC current gain. In this paper, we investigate the underlying physical mechanism of base and collector current degradation with the help of TCAD device simulation. We chose the HICUM model level2 for the modeling purpose to evaluate the drift of model parameters according to stress time. The evolution of the model parameters is described with suitable equations to achieve a physics based compact electrical aging model. The aging laws and the parameter evolution equations with stress time are implemented in compact electrical aging model which allows us to simulate the impact of device failure mechanisms on the circuit in operating conditions.     

一个新的pMOSFET栅电流退化模型

研究了最大栅电流应力 (即 p MOSFET最坏退化情况 )下 p MOSFET栅电流的退化特性 .实验发现 ,在最大栅电流应力下 ,p MOSFET栅电流随应力时间会发生很大下降 ,而且在应力初期和应力末期栅电流的下降规律均会偏离公认的指数规律 .给出了所有这些现象的详细物理解释 ,并在此基础上提出了一种新的用于 p MOSFET寿命评估的栅电流退化模型     

Degradation of DC characteristics of InGaAs/InP singleheterojunction bipolar transistors under electron irradiation

The effects of high-energy (~1 MeV) electron irradiation on the dc characteristics of InGaAs/InP single heterojunction bipolar transistors (SHBT's) are investigated. The device characteristics do not show any significant change for electron doses <10¹⁵/cm². For higher doses, devices show a decrease in collector current, a degradation of common-emitter current gain, an increase in collector saturation voltage and an increase in the collector output conductance. A simple SPICE-like device model is developed to describe the dc characteristics of SHBT's. The model parameters extracted from the measured dc characteristics of the devices before and after irradiation are used to get an insight into the physical mechanisms responsible for the degradation of the devices     

Fundamental narrow MOSFET gate dielectric breakdown behaviors and their impacts on device performance

The post-breakdown (BD) degradation of ultrathin gate oxide Si MOSFET devices is studied by electrical characterization, cross-sectional transmission electron microscopy (TEM) analysis, and theoretical simulation. It is shown that MOSFET devices can remain functional even if a physically direct short between the gate electrode and Si substrate is established. On the other hand, a device can suffer from total failure while no physical damages can be observed under TEM. The physical location of the BD point is shown to be of critical importance in determining the type of BD and the post-BD electrical characteristics of the device. The ability to precisely categorize the gate oxide BD modes in narrow MOSFETs enables us to reevaluate the impact of the gate dielectric BD on the post-BD device performance, and its influence at the circuit levels.     

Hot carrier induced device degradation in RF-nMOSFET's

This study presents the hot carrier induced device degradation in 0.8 μm RF-nMOSFET's within the general framework of the degradation mechanism. It has been found that the device degradation model of a single-finger gate MOSFET could be applied for a multi-finger gate RF-nMOSFET. The reduction of the cut-off frequency and maximum frequency after stress can be explained by the decrease of transconductance and the increase of drain output conductance.     

On the electrical monitor for device degradation in the CHISEL stress regime

This paper reports a complete characterization of hot carrier-induced degradation in the CHannel Initiated Secondary ELectron (CHISEL) regime covering a large set of different stress bias conditions. Using several physical and electrical parameters, our results demonstrate that in the CHISEL regime, differently from the channel hot electrons case, the device degradation is univocally related to the gate current independently of the drain, source, substrate bias, and of the oxide electric field. The gate current is thus identified as the electrical monitor for device degradation in the CHISEL stress conditions.     

A physical-based analytical model for hot-carrier inducedsaturation current degradation of p-MOSFET's

The delay time of a CMOS inverter is directly related to the p-MOSFET saturation current. An accurate aging model for the saturation current is essential for the modeling of the CMOS inverter degradation. In this paper, we report that the saturation current degradation proceeds logarithmically in stress time. A physical analytical model, based on the pseudo-two-dimensional model, is derived for the first time to describe the saturation current degradation under various stress and measurement conditions. There are no empirical parameters in the model. Two physical parameters, the capture cross section and the density of states of electron traps, can be determined independently from the measured degradation characteristics. The simple expression is highly recommended for the modeling of the degradation of the digital CMOS circuits     

New experimental findings on hot carrier effects in deep submicrometer surface channel PMOS

The correlation between gate current and substrate current in surface channel(SC) PMOS with effective channel length down to 0.15 μm is investigated within the general framework of the lucky-electron model. It is found that the impact ionization rate increases, but the device degradation is not serious in deep submicrometer PMOS. To extend the lucky-electron model to deep submicrometer regime, we empirically model the effective pinch-off length as a function of the gate length and the gate bias voltage. SCIHE is suggested as the possible physical mechanism for the enhanced impact ionization and the gate current reduction.     

光电耦合器电流传输比的噪声表征

光电耦合器中可俘获载流子的陷阱密度是影响其电流传输比(CTR)的重要因素,并与器件可靠性有密切关系.在器件内部的多种噪声中,1/f噪声可有效地表征器件陷阱密度.本文在研究光电耦合器工作原理以及1/f噪声理论的基础上,建立了光电耦合器的CTR表征模型和1/f噪声模型.在输入电流宽范围变化的条件下,测量了器件的电学噪声和CTR变化,实验结果验证了以上模型的正确性.将CTR模型与噪声模型相结合,得到了CTR与1/f噪声之间的关系.此关系应用于对光电耦合器辐照实验结果的分析,实验结果与理论得到的结论一致.理论与实验结果表明,噪声幅值越大,电流指数越接近于2,则器件的可靠性越差,相同工作条件下CTR的老化衰减量越大,其失效率显著增大.从而证明噪声可表征光电耦合器的CTR并能准确地反映器件的可靠性.