Relationship between wafer fracture reduction and controlling during the edge manufacturing process

Given the trend towards wafers of a larger diameter, microelectronics circuits are driven by modern IC manufacturing technology. Silicon wafer breakage has become a major concern of all semiconductor fabrication lines because silicon wafer is brittle and high stresses are induced in the manufacturing process. Additionally, the production cost is increasing. Even a breakage loss of a few per cent drives up device costs significantly if wafers are broken near completion, but wafer breakage even near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength empolying a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.This work presents an approach for characterizing silicon wafer failure strength using a simple drop test, to improve our understanding of the stress accumulated in wafer bulk before failure. However, this work will describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unknown reasons. According to an analysis based on the material mechanical theory for the bevel lengths (A1, A2), the edge length and the bevel angle (θ) are optimized to design the edge profile of the produced wafer, to prevent wafer breakage. Restated, when proper material and process control techniques are utilized, silicon wafer breakage should be prevented. This work is the first to demonstrate the importance of understanding wafer strength using a simple mechanical approach.     

Process-induced stress and microcrack nucleation in GaAs wafers

Breakage of GaAs wafers during device fabrication leads to reduced yield and decreased quality control. Historically, wafer breakage that is not attributable to human or equipment errors has been assumed to be due to poor quality wafers. We present evidence that the probability of breakage during sub-micron GaAs device fabrication is a function of dielectric film edge stress, and not necessarily dependent on the magnitude of a critical flaw in the as-received wafer. X-ray residual stress measurements, x-ray topographic imaging, and three-point bend fracture measurements are used to determine the nature and origin of wafer breakage during those fabrication steps which induce large mechanical or thermal stresses. Our data show that the processing sequences that most influence wafer breakage are SiN passivation deposition and rapid thermal annealing implant activation. These processes are primarily responsible for large residual stresses developed in the near-surface layers of the GaAs substrate. For microelectronic applications, the existence of high film edge stresses nucleates microcracks, which further reduces fracture strength. The combined effects of high residual stress and low fracture strength make SiN passivated wafers more fragile (as compared to SiON passivated wafers), and therefore more likely to break during device processing.     

用单片清洗设备进行晶圆背面清洗

晶圆背面的污染降低了半导体器件的成品率,而当器件进入100nm技术节点之后成品率的降低便显得尤为重要。因此,目前众多的器件制造厂家就要求在进行片子正面清洗的同时对其背面也能够实现清洗。由Akrion公司制造的Mach2HP系统就是这样一种单片清洗设备,它具有清洗晶圆正反两面的功能。在起初评价时,设备经过了大量的粒子去除效率的变化。这种大量的变化使我们不能了解这种设备真实的清洗能力。氮化硅(Si3N4)粒子污染的晶片被用以进行粒子去除效率测试。我们发现有Si3N4粒子的晶片引起了背面粒子去除效率的变化。这种含Si3N4粒子的晶片是通过在裸芯片上沉积Si3N4粒子而特意准备的。我们发现,一些较大的Si3N4粒子在晶片清洗时又分解成更小的粒子。如若在清洗之后分解的粒子仍保留在晶片上,它们便会降低晶片总的粒子去除效果。因此,在这些粒子沉积到晶片上之前,这些粒子群需要进一步分解成实际的粒子。经过了解晶片的预习处理,我们实现了这种清洗设备背面清洗效果的评价。     

An automated loading and unloading system for a maglev wafertransport path

An automated loading and unloading system for placing silicon wafers on a carrier is discussed. Interest is particularly focused on the automated loading of wafers onto a carrier which is moved along a transport path using a magnetic levitation (maglev) drive mechanism. The system consists of a wafer carrier which can move along the path and is purely passive, and a loading and unloading device which uses vacuum and electrical power. A magnetic clamping mechanism presents the wafer from sliding when the carrier moves along the path. The electromagnetic loading and unloading device firmly holds the wafer using vacuum suction and may be carried out by a robot. Only the bottom surface and edge of the wafer are touched by the carrier and the loader-unloader. The loader-unloader described, when combined with a maglev transport path, is potentially useful for connecting the processing tools in a cluster or connecting the workstations along a semiconductor fabrication line     

Experiment study on electroplated diamond wire saw slicing single-crystal silicon

This paper conducted the slicing experiments of single-crystal silicon using a reciprocating electroplated diamond wire saw. The machined wafer topography and wire wear were observed by using scanning electron microscope (SEM). The influences of process parameters and cutting fluids on single-crystal silicon wafer surface roughness (SR), subsurface micro-crack damage (SSD) depth, total thickness variation (TTV) and warp were investigated. The bonded interface sectioning technique was used to examine the cut wafers SSD depth. Study results show that a higher wire speed and lower ingot feed speed can produce lower wafer SR and SSD; the lower warp of wafer needs lower wire speed and ingot feed speed; and low wafer TTV can be obtained by an appropriate matching relationship between wire speed and ingot feed speed. The synthetic cutting fluid has a better total effect to improve the wafer quality. The pulled-out of diamond abrasives is the main wear form of wire, which indicates that more research on improving the abrasives retaining strength on wire surface should be investigated in fixed-abrasive wire manufacturing process, in order to improve the wire life and wire saw machining process.     

Prediction of the thickness for silicon wafers sawn by diamond wire saw

A higher yield and lower processing cost for the production of the silicon wafer can be realized by reducing the sliced thickness. However, a larger fracture probability is accompanied with the thinner silicon wafer, which limits the wafer thickness to be reduced. The contradiction between reducing wafer thickness and keeping a smaller fracture probability is an important problem for the industrial production of the silicon wafer. This paper investigates the influences of silicon wafer size and machining defects on the fracture probability in order to understand the essential relationship between damage information and fracture probability adequately. A theoretical model of the fracture probability for silicon wafer is proposed based on the probabilistic fracture mechanics to determine a proper thickness for wafers with different size. Furthermore, one method of predicting a proper thickness for silicon wafers sawn by diamond wire saw is developed. The thickness of 450-mm silicon wafer obtained by this proposed method is 920 µm, which is comparable with the value 925 µm specified by the International Technology Roadmap for Semiconductor. The comparison of these two values reveals the feasibility and correctness of this proposed method. The proposed model in this paper can be used to evaluate the fracture probability and predict a proper thickness for silicon wafers with different size, which is benefit to optimize the processing technology and decrease the breakage ratio for the wafer production.     

超薄硅双面抛光片抛光工艺技术

MEMS器件、保护电路、空间太阳电池等的制作需要使用硅双面抛光片,并且要求抛光片的厚度很薄,传统的硅抛光片加工工艺已经不能满足这一要求.介绍了一种用于超薄硅单晶双面抛光片加工的抛光工艺方法.通过对硅片抛光机理[1],抛光方式、抛光工艺的研究和对抛光工艺试验结果的分析,解决了超薄硅单晶双面抛光片在加工过程中碎片率高、抛光...     

基于DOE优化光学玻璃晶片边缘磨削工艺

在光电器件的制造过程中,用光学玻璃晶片作为电路制作的基板材料。玻璃晶片通过在大面积的玻璃面板上划圆获得。划圆后会形成非常锐利的边缘,需要将锐利边缘磨削成圆弧形,以减少在后续加工中产生破损、崩边。在光学玻璃晶片的边缘磨削中,合适的玻璃晶片边缘磨削参数对于晶片边缘磨削后的崩边情况、磨削斜面宽度、中心误差等均有很大影响。利用DOE试验方法,光学玻璃晶片边缘磨削过程中有效减小崩边,并给出了影响因素,获得并验证了最优化的磨削工艺参数,减少了晶片磨削后的崩边破损。     

Wafer temperature measurement in a rapid thermal processor with modulated lamp power

Pyrometry methods utilizing modulated lamp power (“ripple”) were used to improve wafer temperature measurement and control in rapid thermal processing (RTP) for silicon integrated circuit production. Data from a manufacturing line where ripple pyrometers have been tested show significantly reduced wafer to wafer and lot to lot variations in final test electrical measurements and increased yields of good chips per wafer. The pyrometers, an outgrowth of Accufiber’s ripple technique, are used to compensate for ordinary production variations in the emissivities of the backsides of wafers, which face the pyrometers. Power to the heating lamps is modulated with oscillatory functions of time at either the power line frequency or under software control. Fluctuating and quasi-steady components in detected radiation are analyzed to suppress background reflections from the lamps and to correct for effective wafer emissivity. Sheet resistances of annealed wafers with high dose shallow As implants were used to infer temperature measurement capability over a range in backside emissivity. Emissivities are varied when depositing or growing one or more layers of silicon dioxide, silicon nitride, or polycrystalline silicon on the backsides of the wafers.     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.     

Application of Scanning Capacitance Microscopy on SOI device with wafer edge low yield pattern

As semiconductor technology keeps scaling down, many advanced technology and process were applied in the semiconductor process. Especially for the application of IOT (internet of thing) technology, the low leakage and low power consumption product was the key component for this kind of application. SOI (Silicon-On-Insulator) wafer process is one of the advanced and important branches of the semiconductor manufacturing process. Its intrinsic advantage, low leakage and lower power consuming make it very suitable for personal communication device and IOT which match well with the application requirement. As is well known the SOI wafer is different form the normal bulk silicon wafer. The active sits on the silicon oxide insulator, which makes the final device separate from the substrate. Basically, all of the devices are floating on a nonconductive oxide layer. It comes with many challenges for process and analysis as compared with the conventional bulk silicon process.The most conventional analysis method is not applicable in the SOI device such as the PVC (passive voltage contrast) and current image methodology which are a very powerful and important in the failure analysis.In this paper, scanning capacitance is successfully used as the substitution of the PVC method. The SCM (Scanning Capacitance Microscopy) is a complicated process. Since all of the abnormality or physical change will affect the measured capacitance, then the capacitance signal will theoretically has many information with itself, including open, short and leakage. Through the detailed study, the contact level top-down SCM was successfully applied on the SOI unit. By proper setting of SCM bias condition, it can not only visualize the possible leaky location but also can reveal the possible path. Further nanoprobing and TEM (Transmission Electron Microscopy) have confirmed the SCM analysis.     

单晶硅生产工艺中的关键技术

电子技术已经成为一个国家的技术发展状况的重要指针。在半导体芯片中,单晶硅材料占据了整个芯片体积的约99%。单晶硅的生产技术和产量体现了一个国家在半导体行业中的发展水平。通过对单晶硅原材料制造工艺的细致分析,把制程工艺中的关键控制参数分类为"静态"控制参数和"动态"控制参数,提出了运用科学实验,建立数学模型和编制控制程序的生产控制方法,以取得品质、成本的双重控制。     

Photoresist deposition without spinning

A technique for resist deposition using a novel fluid ejection method is presented in this paper. An ejector has been developed to deposit photoresist on silicon wafers without spinning. Drop-on-demand coating of the wafer reduces waste and the cost of coating wafers. Shipley 1400-21, 1400-27, 1805, and 1813 resists were used to coat sample 3- and 4-in wafers. Later, these wafers were exposed and developed. The deposited resist film was 3.5 /spl mu/m thick and had a surface roughness of about 0.2 /spl mu/m. The ultimate goal is to deposit resist films with a thickness of the order of 0.5 /spl mu/m and a surface roughness of the order of 30 /spl Aring/, which is currently achieved for 200-mm silicon wafers by using a spinning method. Such goals can be attained by using micromachined multiple ejectors or with better control over the deposition environment. In the micromachined configuration, thousands of ejectors are made into a silicon die, as presented by Percin et al. (2002), and thus allow for a full coating of a wafer in a few seconds. Coating in a clean environment will allow the lithography of circuits for microelectronic applications. Other potential applications for the technology in the semiconductor manufacturing are in deposition of low-k materials, wafer cleaning, manufacturing of organic LEDs and organic FETs, direct lithography, nanolithography, and coating for hard-disk drives.     

Characterization of Generation Lifetime and Surface Generation Velocity of Semiconductor Wafers by a Contactless Zerbst Method

A contactless Zerbst method has been developed to characterize the generation lifetime and the surface generation velocity of a semiconductor wafer. This characterization is unaffected by the gate leakage current or the device fabrication process. In this study, this contactless Zerbst method was used to characterize the generation lifetime and the surface generation velocity of a partially Au-doped Si wafer. The results demonstrate that the contactless Zerbst method is a powerful technique for characterizing the generation lifetimes and the surface recombination velocities of semiconductor wafers.     

Crystalline damage in silicon wafers and 'rare event' failure introduced by low-energy mechanical impact

We used X-ray diffraction imaging to detect and characterize mechanical damage introduced to 300 mm silicon wafers by low impact energy exerted on the wafer edge. Maps of crystalline damage show a correlation between the damage size, the magnitude of the impact energy and the location of the impact point. We demonstrate the existence of crystalline non-visual defects; crystalline defects that appear in the X-Ray diffraction images but not in optical microscopy or scanning electron microscope. We propose a mechanism of crystalline damage formation at low impact energies based on finite element analysis and high-resolution synchrotron white beam transmission X-ray topography. Finally, we propose the concept of 'rare-event' to described relatively low rate of occurrence of wafer failure by fracture within semiconductor manufacturing facilities.     

Prestressed Ceramic Coatings for Enhanced Reliability of Silicon Wafer Fracture Strength

The objective of this paper is to investigate thin, solid, prestressed ceramic films as a means of enhancing the reliability of silicon semiconductor wafers stressed in bending. To characterize the effect of thin films on strength, one-micrometer ceramic films were deposited on wafers using plasma-enhanced chemical-vapor deposition. The modulus of rupture (MOR) of the coated wafers was determined from four-point bend testing of coated samples. Adhesion testing of the coated wafers primarily showed cohesive rather than adhesive failure. A series of residual stresses was introduced into the coating-silicon interface and the MOR was determined. The results showed that for a thin brittle coating (1 mum) on a silicon wafer (635 mum), the minimal shear stress at the surface led to dominance of the residual stress over intrinsic coating strength as the critical parameter affecting failure. A correlation between MOR and residual stress was established.     

Full Field Temperature Measurement of Specular Wafers During Rapid Thermal Processing

Many of the processes involved in the creation of semiconductor devices involve high-temperature processing of silicon wafers. The benefits of reduced thermal budget and faster cycle time make rapid thermal processing (RTP) a possible key technology for semiconductor manufacturing. However, the problem of nonuniform wafer temperature has prevented it from further spread among the industry. The first step in developing controls to maintain a uniform wafer temperature is accurate temperature measurement during processing. In this paper, a system was developed to exploit the specular reflectivity of silicon wafers and obtain a measurement of the wafer temperature profile. The spectral reflectivity is determined by measuring the intensity of an incident beam and the beam reflected from the wafer surface. With this measured reflectivity value the spectral-directional wafer emissivity was determined using Kirchhoff's law. The obtained emissivity then was used to calculate the wafer temperature profile from an image obtained with an infrared camera. An experimental study of the transmittance of an undoped silicon calibration wafer at an elevated temperature is also discussed     

电磁驱动柔性振动膜无阀微泵

提出了一种新型微泵设计方案和制作工艺，将电磁驱动器与大振幅振动膜相结合，得到流量大、易于控制的新型微泵。该微泵结构简单，由硅橡胶(聚二甲基硅氧烷PDMS橡胶)振动膜和无阀泵泵体组成，将硅加工工艺和非硅加工工艺(电镀)相结合。采用电镀和硅橡胶加工方法将振动膜直接制作在一个硅片上；用电镀和体硅加工工艺将驱动线圈和无阀泵泵体制作在另一块硅片上，然后将两个硅片键合在一起。对该微泵的性能特点正进行着更深入的研究。     

高温离子注入靶盘设计

简要介绍了高温离子注入靶室的设计。通过设计辅助加热装置使离子注入时晶片表面温度达到500℃以上,并通过靶盘旋转和往返平移扫描的方式实现了晶片片内和片间的温度均匀性,满足了碳化硅掺杂、SOI晶片制造等特殊需要。     

A directed-graph classifier of semiconductor wafer-test patterns

A technique for training an expert system for semiconductor wafer fabrication process diagnosis is described. The technique partitions an existing set of electrically tested semiconductor wafers into groups so that all wafers within each group have similar spatial distributions of the electrical test data across selected die sites. The spatial distribution of test data from the selected die sites on each wafer is referred to as the test pattern of that wafer. A directed graph that is developed by the partitioning algorithm then efficiently classifies a new incoming wafer to one of the groups established during partitioning on the basis of its test pattern. The distribution of known processing histories of wafers within the group to which the new incoming wafer is classified provides a provisional diagnosis of the incoming wafer's process history