Relationship between wafer edge design and its ultimate mechanical strength

Due to its brittle nature, high stress-induced in manufacturing process, silicon wafer breakage has become a major concern for all semiconductor fabrication line. Furthermore, the production cost had increased in advanced technology day by day. Even a some-percent breakage loss drives device costs up significantly if wafers are broken near completion. Consequently, wafer breakage even near the beginning of the process is significant. In short words, silicon wafer breakage has become a major concern for all semiconductor fabrication lines, and so high stresses are easily induced in its manufacture process. The production cost is increasing even breakage loss of a few percent significantly drives device costs up, if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength employing a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.A physical model would also be proposed to explain the results. This model demonstrates that the fracture rate of wafers can be reduced by controlling the uniformity of the difference between the front and rear bevel lengths during the wafer manufacturing process.     

Relationship between wafer fracture reduction and controlling during the edge manufacturing process

Given the trend towards wafers of a larger diameter, microelectronics circuits are driven by modern IC manufacturing technology. Silicon wafer breakage has become a major concern of all semiconductor fabrication lines because silicon wafer is brittle and high stresses are induced in the manufacturing process. Additionally, the production cost is increasing. Even a breakage loss of a few per cent drives up device costs significantly if wafers are broken near completion, but wafer breakage even near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength empolying a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.This work presents an approach for characterizing silicon wafer failure strength using a simple drop test, to improve our understanding of the stress accumulated in wafer bulk before failure. However, this work will describe many of the improvements that have resulted in the virtual elimination of wafer breakage due to unknown reasons. According to an analysis based on the material mechanical theory for the bevel lengths (A1, A2), the edge length and the bevel angle (θ) are optimized to design the edge profile of the produced wafer, to prevent wafer breakage. Restated, when proper material and process control techniques are utilized, silicon wafer breakage should be prevented. This work is the first to demonstrate the importance of understanding wafer strength using a simple mechanical approach.     

The Effect of Thermal Shocks on the Stresses in a Sapphire Wafer

Sapphire wafers can experience temperature variations during processing in a furnace, which in turn can cause large deformation and stresses in the wafers. This paper aims to reveal the mechanism of stress development and evolution in sapphire wafers during thermal shocks, as well as the dependence of the stresses on some process parameters. Finite-element stress analysis was conducted on a single sapphire wafer subjected to thermal shocks. The results show that the thermal gradient in the radial direction induces high stresses even in mechanically unrestrained wafers. The largest stress components occur at the wafer edge as the largest normal stresses are circumferential; whereas the maximum tensile stress is realized upon cooling, the highest value of the maximum shear stress and the minimum compressive stress eventuate in the heating-up phase. The normal stresses have a parabolic distribution in the radial direction. It was found that holding the furnace temperature leads to a more uniform temperature distribution across the wafer but brings about higher tensile stresses in the cooling phase     

The effect of patterns on thermal stress during rapid thermalprocessing of silicon wafers

The presence of patterns can lead to temperature nonuniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Plastic deformation of the wafer can lead to production problems such as photolithography overlay errors and degraded device performance. In this work, the transient temperature fields in patterned wafers are simulated using a detailed finite-element-based reactor transport model coupled with a thin film optics model for predicting the effect of patterns on the wafer radiative properties. The temperature distributions are then used to predict the stress fields in the wafer and the onset of plastic deformation. Results show that pattern-induced temperature nonuniformity can cause plastic deformation during RTP, and that the problem is exacerbated by single-side heating, increased processing temperature, and increased ramp rate. Pattern effects can be mitigated by stepping the die pattern out to the edge of the wafer or by altering the thin film stack on the wafer periphery to make the radiative properties across the wafer more uniform     

Transient effects in rapid thermal processing

Using a realistic model of a rapid thermal processing chamber including Navier-Stokes calculations of the gas losses, the stresses and yield strengths of silicon wafers were determined for several linear ramp rates. It was found that the stress to yield strength ratio is a sensitive function of the ramp rate and the radiant uniformity. Radiation patterns that produce good steady-state thermal nonuniformity overheat the wafer edges during heating transients, leading to high stress levels     

Effects of self-aligned electroplating Cu pillar/Sn-xAg bump on dense Al lines for chip-to-package connection

Self-aligned electroplating is applied to form the Cu pillar/Sn-Ag bump for semiconductor device packaging, while passivation SiN cracks are usually observed at the bump edge on the bump of the array (BOA). In this paper, the simulation method was used to investigate the mechanism of SiN cracks and then, the bump process was optimized to improve the mechanical properties of the Cu pillar/Sn-Ag bump. It was found that higher reflow rounds could improve the shear strength due to the large degree of contact between the rugged scallop-like shape of the Cu₆Sn₅ and the Sn-Ag solder. The fracture plane cleaved between the Sn-Ag and Cu₆Sn₅ interface is consistent with the simulation results. The hardness of the Sn‒Ag solder is proportional to the reflow rounds, and the amount of Ag₃Sn phase precipitation within the Sn-Ag solder contributes to the hardness value. In contrast, the disadvantage is that thermal residual stress could deteriorate the SiN crack, especially for a BOA structure The study concludes that an optimal bump process, including Sn-2%Ag solders at 260 °C for 30 s, could obtain a high shear strength and appropriate solder hardness without passivated SiN cracking.     

退火对GaAs窗口晶体力学性能的影响

在L EC Ga As晶片中,存在相当大的弹性应变,在高温退火后,晶片的晶格参数的相对变化量不到原生晶片的70 % ,残余应力得以部分释放,从而减小残余应力诱生断裂的可能性,提高了Ga As晶体的断裂模数.原生Ga As晶体加工的样品的断裂模数平均值约为135 MPa,而退火Ga As晶体加工的样品的断裂模数平均值更高,约为15 0 MPa,断裂模数最高值达16 3MPa.     

手机用GaAs SPDT开关的全离子注入技术

对移动通信用单刀双掷开关制作工艺中的 Ga As全离子注入技术进行了实验比较和讨论 ,认为 76mmGa As圆片经光片注入 Si离子后包封 40 nm Si O2 +60 nm Si N进行快速退火再进行 B离子注入隔离和器件制作的工艺方法先进、工艺简便、表面物理性能好、产品成本低、重复性和均匀性好、成品率高及器件性能优良。     

Mechanical stress as a function of temperature in aluminum films

Mechanical stress in interconnection is a problem of growing importance in VLSI devices. Open circuits due to metal cracking and voiding and short circuits due to hillocks are stress-related phenomena. The origins of this stress are discussed including intrinsic stresses from the synthesis of the films and thermally induced stresses. A measurement technique based on the determination of wafer curvature with a laser scanning device is utilized to directly measure the film stress in situ as a function of temperature during thermal cycling. The changes in stress observed during thermal cycles are interpreted quantitatively and mechanisms that lead to plastic deformation and their relationship to hillocks are discussed. In the stress vs. temperature measurements, several regions have been identified including elastic and plastic behavior both under compression and tension, the yield strength, recrystallization, gain growth, hardening, and solid-state reactions. The effects of deposition conditions on these regions are also examined     

Mechanical strength of 300 mm diameter silicon wafers at high temperatures: modeling and simulation

Under gravitational and thermal constraints of IC process technology, 300 mm diameter silicon wafers can partly relax via slip dislocation generation and propagation, degrading the electrical characteristics of the leading edge device. We present a force balance model to describe the strain relaxation in large wafer diameter, which includes heat transfer effects and the criterion for yielding under a plane stress state. The material attributes, e.g. oxygen and its state of aggregation, are taken into account. While the plastic deformation of silicon wafers caused by thermal stresses at high temperatures can be controlled by process design, the control of plastic deformation due to gravitational forces may be accomplished by equipment design. This system approach allows calculation of wafer mechanics and ramp rate profiles for an arbitrary high-temperature process. The quantitative theory proposed here provides guidance for computer simulation to configure stable slip-free wafer process flow under mechanical and thermal loads. Applications include high speed simulations for use in ‘what if’ experiments or initial simulations of large scale experimental sequences. The simulator developed can also be used by IC manufacturers to determine optimum wafer throughput and cycle times in front-end device processes.     

Fabrication process simulation and reliability improvement of high-brightness LEDs

To enhance the light extraction efficiency and thermal performance of AlGaInP light-emitting diodes (LEDs), the wafer bonding technique which can replace the GaAs substrate with other high thermal conductivity substrates was applied. However, this technique may make the film crack during either the removal etching process of the GaAs substrate or the annealing process after the GaAs removal. Therefore, this crack problem is an important issue in the reliability/yield of high-brightness LEDs. In this research, a detailed finite element model of the high-brightness AlGaInP LED, which is replaced by the GaAs substrate with high thermal conductivity substrate through the Au–In metal bonding technique, was developed and fabricated. In addition, the mechanical behavior of wafer-level metal bonding was also simulated by finite element analysis (FEA) and validated by experimental measurements. Hence, the above validated simulation technique combined with process modeling is used to understand the stress variation of the multilayer structure of AlGaInP LED during the fabrication process and to find the principal cause of the film crack.     

Transient thermal analysis of sapphire wafers subjected to thermal shocks

Rapid heating and cooling are commonly encountered events in integrated circuit processing, which produce thermal shocks and consequent thermal stresses in wafers. The present paper studies the heat transfer in sapphire wafers during a thermal shock as well as the dependence of the wafer temperature on various process parameters. A three-dimensional finite-element model of a single sapphire wafer was developed to analyze the transient heat conduction in conjunction with the heat radiation and heat convection on the wafer surfaces. A silicon wafer was also investigated, for comparison. It was found that the rapid thermal loading leads to a parabolic radial temperature distribution, which induces thermal stresses even if the wafer is not mechanically restrained. The study predicted that for sapphire wafers the maximum furnace temperature of 800 /spl deg/C should be held for two hours in order to get a uniform temperature throughout the wafer.     

An automated loading and unloading system for a maglev wafertransport path

An automated loading and unloading system for placing silicon wafers on a carrier is discussed. Interest is particularly focused on the automated loading of wafers onto a carrier which is moved along a transport path using a magnetic levitation (maglev) drive mechanism. The system consists of a wafer carrier which can move along the path and is purely passive, and a loading and unloading device which uses vacuum and electrical power. A magnetic clamping mechanism presents the wafer from sliding when the carrier moves along the path. The electromagnetic loading and unloading device firmly holds the wafer using vacuum suction and may be carried out by a robot. Only the bottom surface and edge of the wafer are touched by the carrier and the loader-unloader. The loader-unloader described, when combined with a maglev transport path, is potentially useful for connecting the processing tools in a cluster or connecting the workstations along a semiconductor fabrication line     

Prestressed Ceramic Coatings for Enhanced Reliability of Silicon Wafer Fracture Strength

The objective of this paper is to investigate thin, solid, prestressed ceramic films as a means of enhancing the reliability of silicon semiconductor wafers stressed in bending. To characterize the effect of thin films on strength, one-micrometer ceramic films were deposited on wafers using plasma-enhanced chemical-vapor deposition. The modulus of rupture (MOR) of the coated wafers was determined from four-point bend testing of coated samples. Adhesion testing of the coated wafers primarily showed cohesive rather than adhesive failure. A series of residual stresses was introduced into the coating-silicon interface and the MOR was determined. The results showed that for a thin brittle coating (1 mum) on a silicon wafer (635 mum), the minimal shear stress at the surface led to dominance of the residual stress over intrinsic coating strength as the critical parameter affecting failure. A correlation between MOR and residual stress was established.     

Germanium-on-insulator substrates by wafer bonding

Single-crystal Ge-on-insulator (GOI) substrates, made by bonding a hydrogen-implanted Ge substrate to a thermally oxidized, silicon handle wafer, are studied for properties relevant to device fabrication. The stages of the layer transfer process are examined through transmission electron microscopy (TEM) from the initial hydrogen implant through the final Ge film polish. The completed GOI substrate is characterized for film uniformity, surface quality, contamination, stress, defectivity, and thermal robustness using a variety of techniques and found to be acceptable for initial device processing.     

Effect of surface passivation of AlGaN/GaN heterostructurefield-effect transistor

The effect of SiN passivation of the surface of AlGaN/GaN transistors is reported. Current deep level transient spectroscopy (DLTS) measurements were performed on the device before and after the passivation by a SiN film. The DLTS spectra from these measurements showed the existence of the same electron trap on the surface of the device. The DLTS spectrum obtained from the measurement of the passivated device showed a significantly lower peak for this trap. The discrepancy in the DLTS peak amplitude is explained by the effect of the passivation on the surface traps and underlines the surface nature of the major defect noticed in the device     

Prediction of the thickness for silicon wafers sawn by diamond wire saw

A higher yield and lower processing cost for the production of the silicon wafer can be realized by reducing the sliced thickness. However, a larger fracture probability is accompanied with the thinner silicon wafer, which limits the wafer thickness to be reduced. The contradiction between reducing wafer thickness and keeping a smaller fracture probability is an important problem for the industrial production of the silicon wafer. This paper investigates the influences of silicon wafer size and machining defects on the fracture probability in order to understand the essential relationship between damage information and fracture probability adequately. A theoretical model of the fracture probability for silicon wafer is proposed based on the probabilistic fracture mechanics to determine a proper thickness for wafers with different size. Furthermore, one method of predicting a proper thickness for silicon wafers sawn by diamond wire saw is developed. The thickness of 450-mm silicon wafer obtained by this proposed method is 920 µm, which is comparable with the value 925 µm specified by the International Technology Roadmap for Semiconductor. The comparison of these two values reveals the feasibility and correctness of this proposed method. The proposed model in this paper can be used to evaluate the fracture probability and predict a proper thickness for silicon wafers with different size, which is benefit to optimize the processing technology and decrease the breakage ratio for the wafer production.     

The effect of surface roughness on the radiative properties ofpatterned silicon wafers

The radiative properties of patterned silicon wafers have a major impact on the two critical issues in rapid thermal processing (RTP), namely wafer temperature uniformity and wafer temperature measurement. The surface topography variation of the die area caused by patterning and the roughness of the wafer backside can have a significant effect on the radiative properties, but these effects are not well characterized. We report measurements of room temperature reflectance of a memory die, logic die, and various multilayered wafer backsides. The surface roughness of the die areas and wafer backsides is characterized using atomic force microscopy (AFM). These data are subsequently used to assess the effectiveness of thin film optics in providing approximations for the radiative properties of patterned wafers for RTP applications     

Progress in Low-temperature Surface Passivation of Silicon Solar Cells using Remote-plasma Silicon Nitride

Using a remote-plasma technique as opposed to the conventional direct-plasma technique, significant progress has been obtained at ISFH in the area of low-temperature surface passivation of p-type crystalline silicon solar cells by means of silicon nitride (SiN) films fabricated at 350–400°C in a plasma-enhanced chemical vapour deposition system. If applied to the rear surface of the low-resistivity p-type substrates, the remote-plasma SiN films provide outstanding surface recombination velocities (SRVs) as low as 4 cm s⁻¹, which is by a clear margin the lowest value ever obtained on a low-resistivity p-Si wafer passivated by a solid film, including highest quality thermal oxides. Compared to direct-plasma SiN films or thermally grown oxides, the remote-plasma films not only provide significantly better SRVs on low-resistivity p-silicon wafers, but also an enormously improved stability against ultraviolet (UV) light. The potential of these remote-plasma silicon nitride films for silicon solar cell applications is further increased by the fact that they provide a surface passivation on phosphorus-diffused emitters which is comparable to high-quality thermal oxides. Furthermore, if combined with a thermal oxide and a caesium treatment, the films induce a UV-stable inversion-layer emitter of outstanding electronic quality. Due to the low deposition temperature and the high refraction index, these remote-plasma SiN films act as highly efficient surface-passivating antireflection coatings. Application of these films to cost-effective silicon solar cell designs presently under development at ISFH turned out to be most successful, as demonstrated by diffused p-n junction cells with efficiencies above 19%, by bifacial p-n junction cells with front and rear efficiencies above 18%, by mask-free evaporated p-n junction cells with efficiencies above 18% and by MIS inversion-layer cells with a new record efficiency of above 17%. All cells are found to be stable during a UV test corresponding to more than 4 years of glass-encapsulated outdoor operation. © 1997 John Wiley & Sons, Ltd.     

Thermal and stress analysis of semiconductor wafers in a rapidthermal processing oven

Results are presented from studies of heat transfer in a rapid thermal processing (RTP)-type oven used for several semiconductor wafer processes. These processes include: (1) rapid thermal annealing; (2) thermal gradient zone melting; and (3) lateral epitaxial growth over oxide. The heat transfer studies include the measurement of convective heat transfer in a similar apparatus, and the development of a numerical model that incorporates radiative and convective heat transfer. Thermal stresses that are induced in silicon wafers are calculated and compared to the yield stress of silicon at the appropriate temperature and strain rate. Some methods for improving the temperature uniformity and reducing thermal stresses in the wafers are discussed