| 一种高电源抑制比带隙基准源的设计 |
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| 引用本文： | 龚美霞,丁宁.一种高电源抑制比带隙基准源的设计[J].电子测试,2010(9):77-80. |
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| 作者姓名： | 龚美霞 丁宁 |
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| 作者单位： | 南京信息职业技术学院,10046 |
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| 摘 要： | 带隙基准源是LDO中的重要模块,其性能的好坏直接影响到LDO整个系统的性能,为此本文针对以上问题进行相关研究,设计一种具有较高的PSRR和较低的稳定输出电压的带隙基准电压源。文中结合工程实际的要求设计了一款具有高的电源抑制比（PSRR）、低的输出基准电压的带隙基准电压源。本设计采用SMIC公司的0.18μm工艺进行仿真,Hspice的仿真结果表明该基准源在电源抑制比（PSRR）、温度特性等方面有良好的性能。
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| 关 键 词： | CMOS 带隙基准 PSRR |
Design of a bandgap reference with high PSRR |
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| Gong Meixia,Ding Ning.Design of a bandgap reference with high PSRR[J].Electronic Test,2010(9):77-80. |
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| Authors: | Gong Meixia Ding Ning |
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| Affiliation: | Nanjing Institute of Information Technology 10046 |
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| Abstract: | Bandgap reference is a key component of LDO.Its performance has direct impact on the performance of the LDO whole system.This paper proposes a CMOS bandgap reference with high PSRR and low stable output voltage.In combination with the requirements of engineering designed a high power supply rejection ratio（PSRR）,low output voltage of bandgap reference.The design process using SMIC＇s 0.18μm simulation,Hspice simulation results show that the reference source in the power supply rejection ratio（PSRR）,temperature characteristics such as good performance. |
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| Keywords: | CMOS PSRR |
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