高光谱成像用高帧频CMOS图像传感器北大核心

针对高帧频、全局曝光和光谱平坦等成像应用需求,设计了一款高光谱成像用CMOS图像传感器。其光敏元采用PN型光电二极管,读出电路采用5T像素结构。采用列读出电路以及高速多通道模拟信号并行读出的设计方案来获得低像素固定图像噪声(FPN)和非均匀性抑制。芯片采用ASMC 0.35μm三层金属两层多晶硅标准CMOS工艺流片,为了抑制光电二极管的光谱干涉效应,后续进行了光谱平坦化VAE特殊工艺,并对器件的光电性能进行了测试评估。电路测试结果符合理论设计预期,成像效果良好,像素具备积分可调和全局快门功能,最终实现的像素规模为512×256,像元尺寸为30μm×30μm,最大满阱电子为400 ke^(-),FPN小于0.2%,动态范围为72 dB,帧频为450 f/s,相邻10 nm波段范围内量子效率相差小于10%,可满足高光谱成像系统对CMOS成像器件的要求。     

Analytical Modeling for Translating Statistical Changes to Circuit Variability by Ultra-Deep Submicron Digital Circuit Design

This paper presents a physics-based compact gate delay model that includes all short-channel phenomena prevalent at the ultra-deep submicron technology node of 32 nm. To simplify calculations, the proposed model is connected to a compact α-power law-based (Sakurai-Newton) model. The model has been tested on a wide range of supply voltages. The model accurately predicts nominal delays and the delays under process variations. It has been shown that at lower technology nodes, the delay is more sensitive to threshold voltage variations, specifically at the sub-threshold operating region as compared with effective channel length variations above the threshold region.     

Investigation on SCR-based ESD protection device for biomedical integrated circuits in a 0.18-μm CMOS process

In these decades, integrated circuits for biomedical electronics applications have been designed and implemented in CMOS technologies. In order to be safely used by human, all microelectronic products must meet the reliability specifications. Therefore, electrostatic discharge (ESD) must be taken into consideration. To protect the biomedical integrated circuits in CMOS technologies from ESD damage, a dual-directional silicon-controlled rectifier (DDSCR) device was presented in this work. Experimental results show that the DDSCR has the advantages of high ESD robustness, low leakage, large swing tolerance, and good latchup immunity. The DDSCR was suitable for ESD protection in biomedical integrated circuits.     

基于GL0816传感器的高速线阵CMOS相机系统设计

为了满足印刷等高端工业检测中物体快速运动,需要大幅面、高行频、高分辨率图像采集等要求,研发了一款微米级高分辨率、高速线阵工业相机。首先,介绍了高行频、高分辨率国产CMOS图像传感器GL0816的功能与特点。然后,基于该芯片设计了一套高速大幅面高分辨率线阵工业相机系统,该系统采用FPGA作为整个系统的控制核心,以DDR3LSDRAM作为图像缓存器,以GigE vision2.0协议为输出标准,以SFP+作为高速图像输出接口。最后,搭建相机系统测试环境,对所设计的相机进行系统测试。结果表明:该相机系统行分辨率为8 192,可连续采集2 000行作为一帧图像输出,行频为50kHz,动态范围为57.32dB,信噪比为40.95dB,具有实时图像采集功能。该相机系统具有大幅面、高帧频、高分辨率、高信噪比、宽动态范围等优点,适用于印刷检测行业快速运动目标捕获成像及图像实时显示。     

A New Design Methodology for Time-Based Capacitance-to-Digital Converters (T-CDCs)

This paper introduces a 9-bit time-based capacitance-to-digital converter (T-CDC). This T-CDC adopts a new design methodology for parasitic cancellation with a simple calibration technique. In T-CDCs, the input sensor capacitance is first converted into a delay pulse using a capacitance-to-time converter (CTC) circuit; then this delay signal is converted into a digital code through a time-to-digital converter (TDC) circuit. A prototype of the proposed T-CDC is implemented in UMC 0.13 μm CMOS technology. This T-CDC consumes 8.42 μW and achieves a maximum SNR of 45.14 dB with a conversion time of 1 μs that corresponds to a figure of merit (FoM) of 16.4 fJ/Conv.     

Sizing of multi-stage Op Amps by combining design equations with the gm/ID method

Analog integrated circuit design has as integral parts both analytical reasoning and numerical validation in the process from topology construction to sizing. Given a circuit topology, different circuit sizing results can be obtained from different processes of sizing inference. Sizing methods by simulation-based numerical searching have been a continuously studied subject. However, almost all approaches in this category require an overwhelming number of circuit simulations to arrive at an optimized sizing result. On the other hand, many published manual sizing methods by using the conventional device equations also require repeated SPICE simulations to correct the equation-based sizing results. This paper proposes a systematic gm/ID-based initial sizing method specifically customized for designing multiple-stage operational amplifiers (Op Amps). A main feature of the proposal is to use circuit-level design equations as constraints on the gm/ID table lookup method to substantially reduce the uncertainty in the sizing calculations. As a result, a significant amount of SPICE based correction work can be reduced to complete an initial sizing. The proposed sizing procedure includes a few regular sizing rules customized to the configuration of multi-stage Op Amps. We validate the proposed sizing method by application to several multi-stage Op Amp examples with a capacitive load or Miller compensation. Simulations have justified that the produced initial sizing results can achieve most of the prespecified design targets.     

Harmonic fold back reduction at the N‐path filters

In this paper, a method is proposed to reduce harmonic fold back (HFB) problem of N‐path filters, without increasing the input reference clock (f_CLK ) frequency. The HFB at the N‐path filter is analyzed, and simple expressions are extracted to model this problem. Using the results of the analysis, an M‐of‐N‐path filter has been proposed that behaves like an M × N‐path filter in terms of HFB problem; however, the f_CLK frequency of this structure is the same as an N‐path filter. To demonstrate the feasibility of the proposed idea, a 3‐of‐4‐path filter is designed, and its characteristics are compared with 4‐path and 12‐path filters by simulation. Impacts of different non‐idealities like clock‐phase error, mismatch, and parasitic capacitance are investigated. The transistor‐level implementation of this filter is performed in 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) technology. The simulation results show that the filter has the pass‐band gain of 17 dB, tuning range of 0.2–1.2 GHz, −3 dB bandwidth of 25 MHz, quality factor of 8–48, 18 dB out‐of‐band rejection, 16 dB rejection of the third harmonic of switching frequency (f_s ), and the noise figure of 4.35 dB (using ideal G_m cells) and 6.95 dB (for practical G_m cells). The strongest harmonic folding to the filter pass‐band occurs around 11f_s with the attenuation of 23.8 dB. Each G_m cell draws about 12.4 mA from 1.8 V supply, and the out‐of‐band IIP3 and P _{1 dB,CP} are 17 and 4 dBm, respectively. Copyright © 2016 John Wiley & Sons, Ltd.     

Fractional‐order electronically controlled generalized filters

Novel topologies of fractional‐order generalized filters are introduced in this paper. These offer the following benefits: (1) realization of lowpass, highpass, bandpass, allpass, or bandstop filter functions by the same topology; (2) resistorless realizations; (3) electronic adjustment of their frequency characteristics as well as their order; and (4) employment of only grounded capacitors. All the above have been achieved using Operational Transconductance Amplifiers as active elements and appropriate multi‐feedback topologies. The behavior of the proposed designs is verified through simulation results using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35‐µm complementary metal–oxide–semiconductor process. Copyright © 2016 John Wiley & Sons, Ltd.     

基于S11639的紫外-可见光谱仪的设计

目前微型紫外光谱仪多采用背向减薄式或镀膜CCD作为感光元件,针对其价格昂贵的问题,提出了将高性价比的CMOS传感器芯片S11639应用于紫外-可见光谱仪中的设计方案,系统采用非对称性的切尔尼-特纳光学系统进行分光处理,利用STM32微处理器芯片配合复杂可编程逻辑器件CPLD来设计电路将数据上传到上位机,进行光谱图像显示。通过实验对比,验证了用该方案设计的微型紫外-可见光纤光谱仪,具有良好的紫外敏感性,频谱范围为200~900nm,分辨率可达1.5nm。     

LED微显示技术

LED微显示是一种基于芯片上集成高密度二维发光二极管阵列的全固体主动发光器件,其拥有系统设计简单、光能利用率高、响应速度快及工作温度范围宽等优点。主要介绍了LED微显示技术实现方式、最新进展及其应用前景。