| 2GS/s 6-bit 自校准快闪ADC |
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| 引用本文： | 张有涛,李晓鹏,张敏,刘奡,陈辰.2GS/s 6-bit 自校准快闪ADC[J].半导体学报,2010,31(9):095013-5. |
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| 作者姓名： | 张有涛 李晓鹏 张敏 刘奡 陈辰 |
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| 摘 要： | A single channel 2-GS/s 6-bit ADC with cascade resistive averaging and self foreground calibration is demonstrated in 0.18-μ m CMOS. The calibration method based on DAC trimming improves the linearity and dynamic performance further. The peak DNL and INL are measured as 0.34 and 0.22 LSB, respectively. The SNDR and SFDR have achieved 36.5 and 45.9 dB, respectively, with 1.22 MHz input signal and 2 GS/s. The proposed ADC, including on-chip track-and-hold amplifiers and clock buffers, consumes 570 mW from a single 1.8 V supply while operating at 2 GS/s.
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| 关 键 词： | ADC 自校准 GS 闪速 CMOS 动态性能 标定方法 SFDR |
A 2-GS/s 6-bit self-calibrated flash ADC |
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| Zhang Youtao,Li Xiaopeng,Zhang Min,Liu Ao and Chen Chen.A 2-GS/s 6-bit self-calibrated flash ADC[J].Chinese Journal of Semiconductors,2010,31(9):095013-5. |
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| Authors: | Zhang Youtao Li Xiaopeng Zhang Min Liu Ao and Chen Chen |
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| Affiliation: | National Key Laboratory of Monolithic Integrated Circuits and Modules, Nanjing Electronic Devices Institute, Nanjing 210016, China;Nanjing Electronic Devices Institute, Nanjing 210016, China;Nanjing Electronic Devices Institute, Nanjing 210016, China;Nanjing Electronic Devices Institute, Nanjing 210016, China;National Key Laboratory of Monolithic Integrated Circuits and Modules, Nanjing Electronic Devices Institute, Nanjing 210016, China |
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| Abstract: | |
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| Keywords: | analog-to-digital conversion offset averaging flash interpolation calibration |
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