探测器非线性对微波光子链路性能的影响

提出了一种新的光电探测器（PD）非线性模型,进而分析了PD非线性对系统增益及三阶无杂散动态范围（SFDR3）的影响。实验表明,当调制器的直流偏置角变化时,含PD非线性的实际链路与忽略PD非线性的理想链路相比,信号增益的最大值将下降1．7dB,SFDR3最大值下降3dB,因此在高性能链路中考虑探测器非线性是十分必要的。     

一种提高数模混合信号测试精度的算法

文中论述了一种提高数模混合信号测试（基于DSP信号处理）精度的算法（以下称旋转数据算法）,旋转数据算法是针对数模混合信号测试中异步采样的不连续性导致的频谱泄漏问题,而提出的消除频谱泄漏的算法。旋转数据算法的主要思想是：把数模混合电路的测试信号等效地看成由一个旋转向量在X轴上投影产生,当采样不连续时,采样数据经FFT变换...     

一种用于高精度模数转换器的数字校正算法

本文基于14bi t的ADC设计,提出了一种冗余位为2bi t的算法,相比于传统的方法,它提高了输入动态范围,大大降低了对比较器的要求,从而有效的解决了因为比较器的偏差带来的SFDR的下降。对采用本文算法设计的ADC电路进行了仿真,有效位数达到了13.7bi t,并且具有较低的功耗。     

An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters

In this work an 8-bit DAC is presented which uses a new segmented architecture, where distributed binary cells are re-used in thermometric manner to realize the MSB unit cells. The DAC has been fabricated in 0.18 μm five-metal CMOS n-well process to be embedded in multi-standard reconfigurable wireless transmitters for low-speed applications. The proposed architecture has an inherent ability to reduce midcode glitch like the unary architecture, and the simulated midcode glitch is only 0.01 pV s. Simulation results show that the proposed DAC performs with an integral nonlinearity (INL) of 0.33 LSB and a differential nonlinearity (DNL) of 0.14 LSB. The DAC can achieve a maximum measured SFDR of 65.19 dB for 97.50 kHz signal at a sampling rate of 100 MSPS, without using any calibration or dynamic element matching (DEM) technique. For 1.07 MHz signal the measured SFDR is 56.84 dB at 100 MSPS sampling rate. At 50 MSPS sampling frequency and 146 kHz signal the SFDR of the DAC is 65.90 dB. The measured SFDR at 538 kHz signal is 63.62 dB for a sampling rate of 50 MSPS. Measured third order intermodulation distortion of the DAC is 58.55 dB, for a dual tone test with 1.03 MHz and 1.51 MHz signals at 50 MSPS sampling rate. Low power is also an important aspect in portable wireless devices. For 10.06 MHz signal and 100 MSPS sampling frequency, the power dissipation of the DAC is 20.74 mW with 1.8 V supply.     

采用环型运放的12-bit 40-MS/s采样保持电路设计实现

为了保证模数转换器转换速度和精度,本文基于0.18微米工艺,设计实现了一款应用于12-bit 40-MS/s流水线ADC前端的采样保持电路.所采用的环型结构运放,可以简化设计、且占用面积小;同时,采用绝缘体上硅工艺,可以消除栅压自举开关中开关管的衬偏效应,改善开关的线性度,提高采样保持电路的性能.采样保持电路面积是0.023平方毫米.测试结果表明：在1.5V供电电压下,采样保持电路功耗是3.5mW;在1MHz输入频率、40MHz采样频率下,该采样保持电路无杂散动态范围可以达到76.85dB,满足12-bit 40-MS/s流水线模数转换器应用需求.     

High performance 14-bit pipelined redundant signed digit ADC

A novel architecture of a pipelined redundant-signed-digit analog to digital converter(RSD-ADC) is presented featuring a high signal to noise ratio(SNR), spurious free dynamic range(SFDR) and signal to noise plus distortion(SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC(residue amplification circuit) stages. With the proposed architecture of ADC, SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR obtained is 102.8 dB at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.     

基于线性插值的DDFS中的相位-幅度映射研究

提出了采用线性插值的方法来实现直接数字频率合成器（DDFS）结构中相位到正弦曲线幅度之间的映射（简称“相幅映射”）。该方法使用具有分段连续性质的线性分段来近似正弦函数曲线的第一象限部分；然后根据正弦曲线的象限对称性，重构完整的正弦曲线。文中分析了基于线性插值技术的DDS的频谱特性；然后对基于该方法的DDS的“无杂散动态范围”进行了研究。最后，提出了线性插值系数选择的详细、系统的步骤，从而取得期望的SFDR。     

一种提高无杂散动态范围的多通道信号接收方法

当大功率信号进入接收机后,将迫使模数转换器工作在非线性区,并导致接收信号中含有大量非线性杂散.为了抑制杂散并提高接收机对小信号的侦测能力,提出了一种具有无杂散高动态范围(Spurious-free Dynamic Range,SFDR)的信号接收方法.首先通过两路不同的通道同时接收信号,然后利用信号之间的频率差异识别杂散,最后在频域上通过频点替换方案抑制杂散.仿真与实验结果表明,当输入为双30 kHz窄带大信号时,该方案能使SFDR提升15 dB.     

一种带电流源校准的16bit高性能DAC

设计了一种带电流源校准电路的16 bit高速、高分辨率分段电流舵型数模转换器(DAC)。针对电流舵DAC中传统差分开关的缺点,提出了一种优化的四相开关结构。系统分析了输出电流、积分非线性和无杂散动态范围(SFDR)三个重要性能指标对电流舵DAC的电流源单元设计的影响,完成了电流源单元结构和MOS管尺寸的设计。增加了一种优化设计的电流源校准电路以提高DAC的动态性能。基于0.18μm CMOS工艺完成了该DAC的版图设计和工艺加工,其核心部分芯片面积为2.8 mm^2。测试结果表明,在500 MHz采样速率、100 MHz输入信号频率下,测得该DAC的SFDR和三阶互调失真分别约为76和78 dB,动态性能得到明显提升。     

模数转换系统无杂散动态范围的测量技巧

SFDR是评估ADC模数转换系统的重要指标,往往决定了数据采集和信号处理系统的整体性能,但在实际工程中很难得到准确的测量结果。其原因有对概念的理解问题、测试条件问题、算法问题以及测试技巧问题。总结了多年工程实践的经验,从多个方面分析了影响SFDR准确测量的因素,提出了解决的办法和技巧。根据提示,基本可以测量出满意的ADC模数转换系统的SFDR指标。