High-level parameterizable area estimation modeling for ASIC designs

Architectural design space exploration and early area budgeting for ASIC and IP block development require accurate high level gate count estimation methods without requiring the hardware being fully specified. The proposed method uses hierarchical and parameterizable models requiring minimal amount of information about the implementation technology to meet this goal. The modeling process flow is to: (1) create a block diagram of the design, (2) create a model for each block, and (3) sum up estimates of all sub-blocks by supplying the correct parameters to each sub-model. We discuss the model creation for a few parameterized library blocks as well as three communication blocks and a processor core from real IC projects ranging from 22 to 250 kgates. The average relative estimation error of the proposed method for the library blocks is 3.2% and for the real world examples 4.0%. The best application of this method is early in the design phase when different implementation architectures are compared.     

用于SoC集成的IP核质量评测方法研究

采用IP核进行SoC设计是集成电路的发展趋势。然而,IP核的质量参差不齐,如何选用高质量IP核成为困扰SoC用户的难题。针对IP核可重用的特点及其在SoC集成应用中的难点,提出了一种主客观相结合的IP核质量评测方法。重点描述了主观质量评测方法的实现和客观质量评测方法的策略,实现了主观质量评测平台,并完成一款数模转换IP核的质量评测。     

System fault-tolerance analysis of COTS-based satellite on-board computers

Fault-tolerance analysis reveals possible system behavior under the influence of faults. Such analysis is essential for satellites where faults might be caused by space radiation and autonomous recovery is needed. In this paper we present a statistical simulation approach for fault-tolerance analysis of satellite On-Board Computers (OBCs) that are based on Commercial Off-The-Shelf (COTS) components. Since the logic level of COTS electronics is unknown to satellite designers, a new higher-level fault-tolerance analysis is required. We propose such technique that relies on OBC modeling and fault modeling, based on the modeling principle of Single-Event Upsets (SEUs). For the first time we can compare the efficiency of fault-tolerance techniques implemented in software and Field-Programmable Gate Array (FPGA). In addition, our approach enables to analyze system fault-tolerance at early development stages. In a case study the approach is applied to an OBC with a Microsemi SmartFusion SoC, that executes a satellite attitude control algorithm. The gained statistical simulation results enabled 50% reduction in the hardware overhead of the implemented memory scrubbing technique without loss in fault-tolerance. Our method revealed critical fault-tolerance drawbacks of the initial system design that could have lead to satellite mission failure.     

SOC时代低功耗设计的研究与进展

在片上系统(SOC)时代,芯片内核的超高功耗密度以及移动应用市场对低功耗的无止境需求,使低功耗设计变得日益重要.文章全面系统地介绍了低功耗设计的相关内容,包括背景、原理和不同层次的功耗优化技术,着重介绍了面向SOC的系统级功耗优化技术.通过对已有研究成果按设计抽象层次和系统功能的分析,指出了其优化的全局性不够充分.提出了基于软硬件协同设计的系统功耗优化思路和设计流程,展望了SOC低功耗设计的发展方向.     

System-on-chip design by proof-based refinement

Systems-on-chip (SoCs) and SoC architectures provide a collection of challenging problems related to specification, modelling techniques, security issues and structuring questions. We describe a design methodology integrating the event B method and characterized by the incremental and proof-controlled construction of SoC models. The essence of the methodology is the refinement of models, starting from system requirements and producing event B models for characterizing the system under development. The refinement is a unifying concept that ensures the consistency of the different models produced and our contribution is an illustration through a case study, namely a system for measuring the parameters of audio/video quality in the digital video broadcasting (DVB) set of digital TV standards. The first part is the derivation of an architecture of parameters from the document ETSI TR 101 290 and the validation of the architecture using invariants of B models. The second part is the proposal of B models of the SystemC scheduler and an instantiation of these abstract models of the simulation semantics by parameters of the SystemC codes automatically translated from the B models of the DVB system. Finally, the third part relies upon a proof-based methodology for deriving an operational semantics of a given system that is expressed by an event B model including invariant properties.     

一种基于嵌入式微处理器内核模块的测试

基于可复用的嵌入式IP内核模块的系统级芯片（SoC）设计方法使测试面临新的挑战。文章针对IP内核模块测试断面临的技术难点，介绍了IP核模块实现测试所需要构建的硬件环境和通用结构．并以嵌入ARM微处理器棱的SoC为例，提出了具体的测试解决方案。     

Functional in-circuit characterisation of ΣΔ modulators

A method for the in-circuit functional testing of ΣΔ modulators is described which can be built in large integrated circuits or systems-on-chip. It allows for measuring gain and phase, as well as total harmonic distortion and signal to noise and harmonic distortion ratio parameters. This method can be built in-circuit using existing computational resources, such as digital signal processors or (re)configurable logic, which can therefore be used to implement both mission and test operations. Both simulation and experimental results were obtained which are in close agreement with those expected from the theory.     

加快IC/IP研发,推动系统芯片发展

运用翔实的事实和数据,分析研究集成电路技术和产业发展规律.提出发展我国集成电路(包括IP)产业的竞争力是推动自主可控系统芯片发展的较好途径.     

A Fast Quantitative Analysis and Performance Estimation Method of SoC Bus Architectures

Various multi-layered bus architectures are now being used in the SoC industry. Reckless use of bus layers may result in low utilization of communication resource and waste silicon area. This paper introduces a quantitative analysis at the initial stage of SoC design. The time complexity is examined and it is found that their scale is the order of n to the power of n, or combinatorial, and thus the problem is NP-complete. The paper proposes some heuristic methods through in-depth investigation and applies them to each step of the exploration to reduce the time complexity. The exploration processes and the proposed methods are implemented as a software program and several experiments are performed. From the results, the performance of SNP turns out to be significantly enhanced and achieves 25% enhancement in comparison with a defacto standard bus, AXI. For time complexity, the reduction ratio goes down to 3.7× 10^-6.     

A variable frequency link for a power-aware network-on-chip (NoC)

Although the technology scaling has enabled designers to integrate a large number of processors onto a single chip realizing chip multi-processor (CMP), problems arising from technology scaling have made power reduction an important design issue. Since interconnection networks dissipate a significant portion of the total system power budget, it is desirable to consider interconnection network's power efficiency when designing CMP. In this paper, we present a variable frequency link for a power-aware interconnection network using the clock boosting mechanism, and apply a dynamic frequency scaling (DFS) policy, that judiciously adjusts link frequency based on link utilization parameter. Experimental result shows that history-based DFS successfully adjusts link frequency to track actual link utilization over time, demonstrating the feasibility of the proposed link as a power-aware interconnection network for system-on-chip (SoC).