Design of a fault-tolerant COTS-based bus architecture

This paper describes the authors' approach to using commercial-off-the-shelf (COTS) products in highly reliable systems. The methodology calls for multilevel fault-protection. The methodology realizes that COTS products are often not developed with high reliability in mind. Nevertheless, by using multi-level fault protection, the same level of reliability as the traditional full-custom fault tolerance approach can be achieved. This methodology allows more freedom for design trade-offs among the fault-protection levels, which can result in less complicated designs than the traditional strictly-enforced fault-containment policy. This paper covers the authors' experiences and findings on the design of a fault-tolerant avionics bus architecture comprised of two COTS buses, the IEEE 1394, and the I²C, for the avionics system of X2000 program at the Jet Propulsion Laboratory. The X2000 design is judicious about ensuring the fault-tolerance provisions do not cause the bus design to deviate from commercial standard specifications, so that the economic attractiveness of using COTS is preserved. The hardware and software designs of the X2000 fault-tolerant bus are being implemented, and flight hardware will be delivered to the Europa Orbiter missions. This work provides an example of how to construct a highly reliable system with low-cost COTS interfaces     

Simulating Single Event Transients in VDSM ICs for Ground Level Radiation

This work considers a SET (single event transient) fault simulation technique to evaluate the probability that a transient pulse, born in the combinational logic, may be latched in a storage cell. Fault injection procedures and a fast fault simulation algorithm for transient faults were implemented around an event driven simulator. A statistical analysis was implemented to organize data sampled from simulations. The benchmarks show that the proposed algorithm is capable of injecting and simulating a large number of transient faults in complex designs. Also specific optimizations have been carried out, thus greatly reducing the simulation time compared to a sequential fault simulation approach.     

Nonlinear statistical modeling and yield estimation technique foruse in Monte Carlo simulations [microwave devices and ICs]

A novel nonlinear statistical modeling technique for microwave devices and a new approach to yield estimation for microwave integrated circuits are presented. The statistical modeling methodology is based on a combination of applied multivariate methods with heuristic techniques. These include principal component analysis and factor analysis in conjunction with maximally flat quadratic interpolation and group method of data handling. The proposed modeling approach, when applied to the database of extracted equivalent circuit parameters (ECPs) for a pseudomorphic high electron mobility transistor device, has proven that it can generate simulated ECPs, S-parameters, that are statistically indistinguishable from measured ones. A new yield estimation technique based on a Latin hypercube sampling (LHS) is also demonstrated. The LHS-based simulation is utilized as an alternative to primitive Monte Carlo (PMC) simulation in yield analysis. An equally confident yield estimate based on the LHS method requires only one-fourth of those simulations needed when the PMC technique is used     

Distributed fault-tolerant classification in wireless sensor networks

Fault-tolerance and data fusion have been considered as two fundamental functions in wireless sensor networks. In this paper, we propose a novel approach for distributed multiclass classification using a fault-tolerant fusion rule for wireless sensor networks. Binary decisions from local sensors, possibly in the presence of faults, are forwarded to the fusion center that determines the final classification result. Classification fusion in our approach is implemented via error correcting codes to incorporate fault-tolerance capability. This new approach not only provides an improved fault-tolerance capability but also reduces computation time and memory requirements at the fusion center. Code matrix design is essential for the design of such systems. Two efficient code matrix design algorithms are proposed in this paper. The relative merits of both algorithms are also studied. We also develop sufficient conditions for asymptotic detection of the correct hypothesis by the proposed approach. Performance evaluation of the proposed approach in the presence of faults is provided. These results show significant improvement in fault-tolerance capability as compared with conventional parallel fusion networks.     

Accurate System Voltage and Timing Margin Simulation in High-Speed I/O System Designs

Accurate analysis of system timing and voltage margin including deterministic and random jitter is crucial in high-speed I/O system designs. Traditional SPICE-based simulation techniques can precisely simulate various deterministic jitter sources, such as intersymbol interference (ISI) and crosstalk from passive channels. The inclusion of random jitter in SPICE simulations, however, results in long simulation time. Innovative simulation techniques based on a statistical simulation framework have been recently introduced to cosimulate deterministic and random jitter effects efficiently. This paper presents new improvements on this statistical simulation framework. In particular, we introduce an accurate jitter modeling technique which accounts for bounded jitter with arbitrary spectrum in addition to Gaussian jitter. We also present a rigorous approach to model duty cycle distortion (DCD). A number of I/O systems are considered as examples to validate the proposed modeling methodology.      

A model based approach to fault detection for the reverse path ofcable television networks

We present a model based method for reliably detecting faults in the reverse path of cable amplifier networks. This method has the advantage over traditional fixed-bound fault detection techniques in that it is able to accurately detect changes in signal behaviour while tracking signal changes due to environmental effects. The resulting method provides an increase in the fault detection sensitivity while simultaneously providing a decrease in the false alarm rate. We have implemented a general approach based an using a modeling engine to capture the reverse pilot signal behaviour of cable television amplifiers. Two modeling specific engines were developed for this purpose. The first one is based on the use of feedforward neural networks; the second one is based on the use of statistical analysis techniques. The resulting fault detection system, when employing either modeling engine, was able to provide good temporal localization of the onset of fault conditions along with a clear indication of the presence of the fault through its duration     

Statistical modeling of reliability in logic devices

Due to continuous technology scaling VLSI circuits feature an increasing susceptibility to transient faults. While complete elimination of errors cannot be guaranteed, current mitigation techniques based on circuit improvement or architectural measures cause a large overhead in terms of area and energy consumption. A more efficient possibility to cope with transient faults can be to tolerate hardware errors at low physical levels and handle them at higher system levels. This can be achieved by reusing error handling capabilities – such as channel decoders – or introducing specialized error correction blocks that take advantage of the system characteristics by concentrating the effort on the components and bits most crucial for system operation. To enable this approach the influence of hardware errors on system performance needs to be evaluated, requiring spatial and temporal models of error propagation in the system. Since Monte Carlo simulation of complex systems is not feasible, a statistical modeling technique of logic gates and circuits is introduced. This approach allows modeling of noise and variability influences on logic gates as well as correlation due to reconvergent fan-out with an error of 5% compared to Monte Carlo simulation but with considerably less runtime.     

多拓扑路由在小卫星网络中的容错保护与流量优化

小卫星星座网络需要具有很好的容错抗毁能力,同时对于不同业务流能选择不同的优化路径进行传输。提出使用多拓扑路由技术解决小卫星星座网络的网络保护和流量优化传输问题。在STK和OPNET平台上设计了小卫星星座网络模型和多拓扑路由协议,并进行了仿真实验。仿真结果验证了星座网络的容错保护功能和对不同业务流的多路径路由选择功能。     

具有较大鲁棒度的歼击机容错控制

针对复杂非线性系统被动容错控制问题,提出将AREs与小生境遗传算法相结合的方法。在T-S建模的基础上,这种方法用于搜寻最优控制器。在小生境遗传算法中提出了交叉变异概率的自适应调整律,克服遗传算法早熟的缺点。为了消除T-S建模误差,应用在线可调且具有补偿项的RBFN来消除建模误差。歼击机在多种故障下的仿真表明,此方法能够实现很好的容错控制效果。     

A statistical modeling approach to location estimation

Some location estimation methods, such as the GPS satellite navigation system, require nonstandard features either in the mobile terminal or the network. Solutions based on generic technologies not intended for location estimation purposes, such as the cell-ID method in GSM/GPRS cellular networks, are usually problematic due to their inadequate location estimation accuracy. In order to enable accurate location estimation when only inaccurate measurements are available, we present an approach to location estimation that is different from the prevailing geometric one. We call our approach the statistical modeling approach. As an example application of the proposed statistical modeling framework, we present a location estimation method based on a statistical signal power model. We also present encouraging empirical results from simulated experiments supported by real-world field tests.     

Developments in the Theory and Application of Importance Sampling

The assessment of bit error rate (BER) performance of a digital communication system via computer simulation has traditionally been done using the Monte Carlo method. For very low BER, this method requires excessive computer time. This time can be substantially reduced by using extrapolation based on importance sampling (IS). In applying IS to a complex system, many considerations must be addressed, chief among which is the reliability (variance) of the estimator as a function of the system particulars. We discuss a number of these considerations and, specifically, derive a number of expressions for the variance. We find that the variance improvement may be severely limited by the dimensionality (or memory) of the system. We describe a means for circumventing this limitation through the definition of a statistically equivalent impulse response. For a linear system, this amounts to the ordinary impulse response. The simulation can be structured to estimate the equivalent impulse response using statistical regression. This new approach has been implemented and found to yield significant runtime improvement over conventional importance sampling for linear systems of large dimensionality. We believe this technique will work also for mildly nonlinear systems, as might be encountered in typical satellite Communications.     

CFCET: A hardware-based control flow checking technique in COTS processors using execution tracing

This paper presents a behavioral-based error detection technique called control flow checking by execution tracing (CFCET) to increase concurrent error detection capabilities of commercial off-the-shelf (COTS) processors. This technique traces the program jumps graph (PJG) at run-time and compares it with the reference jumps graph to detect possible violations caused by transient faults. The reference graph is driven by a preprocessor from the source program.The idea behind the CFCET is based on using an external watchdog processor (WDP) and also the internal execution tracing feature available in COTS processors to monitor the addresses of taken branches in a program, externally. This is done without any modification of application programs, thus, the program overhead is zero. This technique is analytically evaluated based on three different fault models. The results show that the error detection coverage varies between 79.74% and 96.43% depending on the different workload programs. The errors are detected with about zero latency. The external hardware overhead is about 3% using the Altera flex 10K30 FPGA and the execution time overhead is between 33.26% and 140.81% for different workload programs. The overheads have been measured experimentally by executing the workloads on a Pentium system.     

合成孔径雷达卫星系统任务分析方法研究

系统地总结了国内外合成孔径雷达(SAR)卫星的发展现状及趋势,提出了大视角双侧视SAR卫星的新概念。针对SAR卫星有效载荷的特点,从用户需求分析和关键约束条件入手,研究了卫星轨道设计与覆盖性能分析方法,总结了雷达波位参数设计和系统性能分析方法,提出了SAR卫星系统星地一体化任务分析方法。通过计算机仿真,对大视角双侧视SAR卫星概念进行了初步可行性分析。     

Discrete Approach to PWL Analog Modeling in VHDL Environment

In this paper a discrete approach to analog modeling is presented. It is a functional-level, piecewise-linear (PWL) technique implemented in the VHDL environment. Since the models are based on some explicit formulas, fully behavioral architectural bodies have been proposed for them. Their most distinguishing features are discussed in detail. The models of practical circuits are illustrated with simulation results.     

A Practical Layer 3 Admission Control and Adaptive Scheduling (L3-ACAS) for COTS WLANs

We propose a practical approach to provide QoS over the existing best-effort Commercial On The Shelf (COTS) IEEE802.11 WLANs using Layer 3 Admission Control and Adaptive Scheduling (L3-ACAS) scheme. This approach enables operators with existing large-scale WLAN deployments to offer QoS control over their networks with minimal disruption, capital expenditure (CAPEX) or infrastructure upgrade. Extensive simulation studies show that with this scheme, the total goodput, flows throughput ratio, packets delay and jitter of the real-time applications such as VoIP and real-time video can be improved significantly. We have also successfully implemented a testbed to evaluate our architecture using the existing COTS hardware and the open source Linux components.     

Neural network modeling and identification of nonlinear channelswith memory: algorithms, applications, and analytic models

This paper proposes a neural network (NN) approach for modeling nonlinear channels with memory. Two main examples are given: (1) modeling digital satellite channels and (2) modeling solid-state power amplifiers (SSPAs). NN models provide good generalization performance (in terms of output signal-to-error ratio). NN modeling of digital satellite channels allows the characterization of each channel component. Neural net models represent the SSPA as a system composed of a linear complex filter followed by a nonlinear memoryless neural net followed by a linear complex filter. If the new algorithms are to be used in real systems, it is important that the algorithm designer understands their learning behavior and performance capabilities. Some simplified neural net models are analyzed in support of the simulation results. The analysis provides some theoretical basis for the usefulness of NNs for modeling satellite channels and amplifiers. The analysis of the simplified adaptive models explains the simulation results qualitatively but not quantitatively. The analysis proceeds in several steps and involves several novel ideas to avoid solving the more difficult general nonlinear problem     

在C30高速信号处理器上实现高分辨频率估计特征分解法

本文对高分辨技术的高速信号处理器实现进行了探索研究，为高分辨实时系统设计提供了重要的实验方法和依据，把高分辨技术研究从理论分析、方法性能研究推进到实际应用．文中设计研制了C30信号处理机，并实现了高分辨频率估计的特征分解法．研究表明，C30高速信号处理器能有效地实现复杂的高分辨算法，高分辨频率估计特征分解法在C30处理器上表现了良好的分辨力和相当高的估计精度．     

System of Systems Approach to Formal Modeling of CPS for Simulation‐Based Analysis

This paper presents a system‐of‐systems (SoS) approach to the formal modeling of a cyber‐physical system (CPS) for simulation‐based analysis. The approach is based on a convergence technology for modeling and simulation of a highly complex system in which SoS modeling methodology, hybrid systems modeling theory, and simulation interoperation technology are merged. The methodology maps each constituent system of a CPS to a disparate model of either continuous or discrete types. The theory employs two formalisms for modeling of the two model types with formal specification of interfaces between them. Finally, the technology adapts a simulation bus called DEVS BUS whose protocol synchronizes time and exchange messages between subsystems simulation. Benefits of the approach include reusability of simulation models and environments, and simulation‐based analysis of subsystems of a CPS in an inter‐relational manner.     

基于HLA的卫星通信仿真技术研究

基于HLA的基本概念和逻辑结构,构建了HLA平台下的卫星通信仿真架构,并描述了卫星通信系统中联邦的成员框架和运行流程设计,以及卫星通信的建模设计,基于此设计框架的仿真系统能够对卫星通信链路进行动态仿真,有效模拟出真实的系统运行环境。