Optimal asymmetrical back plane biasing for energy efficient digital circuits in 28 nm UTBB FD-SOI

In this work we propose an optimal back plane biasing (OBB) scheme to be used in a UTBB FD SOI technology that minimizes the energy per operation consumption of sub threshold digital CMOS circuits. By using this OBB scheme, simulations show that more than 30% energy savings can be obtained with low threshold voltage (LVT) devices in comparison with classic symmetric back plane biasing (SBB) schemes. Additionally, this OBB scheme allows to adjust the performance of the circuit with very small energy penalties. A very simple and intuitive model, for sub threshold digital CMOS circuits, was developed to justify the benefits obtained by OBB. The results predicted by the model are confirmed with extensive simulation results. We show that the OBB approach can be applied easily to a given circuit just based on the information provided by a logic simulation of the circuit (or even an analysis of its structure) and simple electrical simulations of the pMOS and nMOS transistors. Finally, we show that the variability in the energy consumption is improved by using OBB and suggests that new sizing methodologies must be studied to fully benefit from the wide back plane voltage range available in UTBB FD SOI technology for the design of robust energy efficient digital circuits.     

在SOI基上设计实现D/A驱动的高压LDMOS开关电路

设计实现SOI基上带有D/A驱动的高压LDMOS功率开关电路,利用D/A变换的灵活性,运用数字电路与高压模拟电路混合设计方法,实现数字控制的耐压为300V的LDMOS功率开关电路．该功率集成电路芯片的实现,为SOI高压功率开关电路提供了一种更为方便快速的数字控制设计方法,同时也为功率系统集成电路提供了一种有效的实验验证,从而证实了功率系统集成的探索在理论上以及工程上具有一定的可行性．     

部分耗尽SOI体接触nMOS器件的关态击穿特性

分别采用具有硅化物和不具有硅化物的SOI工艺制成了部分耗尽SOI体接触nMOS晶体管.在体接触浮空和接地的条件下测量了器件的关态击穿特性.通过使用二维工艺器件模拟,并测量漏体结的击穿特性,详细讨论和分析了所制成器件击穿特性的差异和击穿机制.在此基础上,提出了一个提高PD-SOI体接触nMOS击穿特性的方法.     

全耗尽SOI MOSFETs阈值电压解析模型

提出了一种新的全耗尽SOI MOSFETs阈值电压二维解析模型.通过求解二维泊松方程得到器件有源层的二维电势分布函数,氧化层-硅界面处的电势最小值用于监测SOI MOSFETs的阈值电压.通过对不同栅长、栅氧厚度、硅膜厚度和沟道掺杂浓度的SOI MOSFETs的MEDICI模拟结果的比较,验证了该模型,并取得了很好的一致性.     

利用改善的体连接技术制备SOI LDMOSFET

对功率器件中常用的体连接技术进行了改进,利用一次硼离子注入技术形成体连接.采用与常规1μm SOI(硅-绝缘体)CMOS工艺兼容的工艺流程,在SIMOX SOI片上制备了LDMOS结构的功率器件.器件的输出特性曲线在饱和区平滑,未呈现翘曲现象,说明形成的体连接有效地抑制了部分耗尽器件的浮体效应.当漂移区长度为2μm时,开态击穿电压达到10V,最大跨导17.5mS/mm.当漏偏压为5V时,SOI器件的泄漏电流数量级为1nA,而相应体硅结构器件的泄漏电流为1000nA.电学性能表明,这种改善的体连接技术能制备出高性能的SOI功率器件.     

Performance of (1 1 0) p-channel SOI-MOSFETs fabricated by deep-amorphization and solid-phase epitaxial regrowth processes

The impact of local deep-amorphization (DA) and subsequent solid-phase epitaxial regrowth (SPER) are studied for the co-integration of devices with hybrid surface orientation. Thin-body p-channel transistors with 20 nm thick film and HfO₂ gate insulator/metal gate along several directions on a (1 1 0) substrate were fabricated and characterized. No deterioration of transconductance or threshold voltage was induced by DA/SPER process. Device co-integration using DA/SPER process is therefore a realistic option. 〈1 1 0〉 channel on (1 1 0) SOI film yields a 200% gain on the current for the (1 0 0) surface orientation. However, the benefit of it decreases with the channel length.     

单模光纤与SOI纳米线波导耦合设计

波导光栅在集成光学发展中扮演着重要的角色。与其他的耦合方法相比,光栅耦合器具有耦合效率高、制备封装成本低、无需芯片端面抛光、可以在任何地方实现信号输入输出等优点,成为纳米光波导最有潜力的耦合方法。本文提出利用OPTIFDTD软件仿真结合MATLAB编程的方法精确计算光栅耦合效率的新方法。仿真分析了光栅的周期、槽深、占空比、SiO2层厚度等光栅参数对耦合效率的影响,并给出了使输入光栅耦合器耦合效率达到42.6%;输出光栅耦合器的耦合效率达到72.3%的一组最佳光栅参数。     

SOI LIGBT抗闩锁效应的研究与进展

概述了绝缘层上硅横向绝缘栅双极晶体管(SOI LIGBT)抗闩锁结构的改进历程,介绍了从早期改进的p阱深p+欧姆接触SOI LIGBT结构到后来的中间阴极SOI LIGBT、埋栅SOILIGBT、双沟道SOI LIGBT、槽栅阳极短路射频SOI LIGBT等改进结构;阐述了一些结构在抗闩锁方面的改善情况,总结指出抑制闩锁效应发生的根本出发点是通过降低p基区电阻的阻值或减小流过p基区电阻的电流来削弱或者切断寄生双极晶体管之间的正反馈耦合。     

基于SOI工艺的高压LED驱动设计

为了解决LED驱动芯片因耐压低而在高压领域应用受限制的问题,将绝缘体上硅（SOI）技术应用到LED驱动的设计中,设计了一款基于SOI工艺的高压LED驱动芯片。首先提出了该驱动的系统框图,并介绍了其工作原理,然后对各重要模块进行了详细的介绍。该LED驱动输入电压范围为40 V～625 V,采用峰值电流模式控制,并提供线性与脉宽调制（PWM）两种调光方式,根据不同应用,外接的LED灯可达十几至上百个不等。采用XFAB 1μm SOI工艺,并使用Cadence的Spectre系列软件进行了仿真。仿真与测试结果验证了该驱动的良好性能。该设计对基于SOI工艺的高压电源管理芯片的设计具有指导意义。     

Study of hybrid orientation structure wafer

Two types of 5μm thick hybrid orientation structure wafers,which were integrated by（110）or（100） orientation silicon wafers as the substrate,have been investigated for 15-40 V voltage ICs and MEMS sensor applications.They have been obtained mainly by SOI wafer bonding and a non-selective epitaxy technique,and have been presented in China for the first time.The thickness of BOX SiO₂ buried in wafer is 220 nm.It has been found that the quality of hybrid orientation structure with（100）wafer substrate is better than that with（110）wafer substrate by"Sirtl defect etching of HOSW".