一种基于非均匀分段线性插值的直接数字频率合成器

提出了一种基于非均匀分段线性插值的直接数字频率合成器（DDFS）的设计方法．在所设计的DDFS的相位幅度转换模块中．通过对正弦函数的0到π/2段进行非均匀分段，然后在每一段中采用线性插值近似实现．采用此方法。在八分段、十四分段情况下DDFS的无杂散动态范围（SFDR）值分别达到64．7dB、73．3dB。     

基于线性插值非均匀采样的DDS任意波形发生器

介绍了DDS任意波形发生器的基本原理,介绍了DDS波形压缩方法,提出了基于非均匀采样线性插值方法来实现的任意波形发生器,并与传统方法进行比较。     

基于BP-GA智能算法流量仪表标定方法的研究

提出一种基于神经网络（BP）-遗传算法（GA）的高精度流量仪表标定方法。该方法首先利用BP网络的非线性映射功能建立流量计特性曲线的网络模型；然后通过遗传算法的自动寻优功能，智能选取流量仪表大流量区域内的特殊标定点，从而确定流量仪表系数K。现实现了基于BP-GA混合智能算法的仿真标定，仿真结果和实际检测数据表明，该方法在提高流量仪表系数精度方面收到了很好的效果。     

一种新的按位块分段快速排序算法

针对分段快速排序法因分段映射策略不理想而造成算法复杂度显著增加之问题，文章提出了一种由按位块分段、分段映射和局部快速排序所组成的新排序算法——按位块分段快速排序法（以下简称为“按位块分段快速排序”）。算法分析和实验结果都表明：在待排序数据均匀分布或正态分布的情况下，按位块分段快速排序法的时间复杂度可以达到O（N），而附加存储空间开销却仅仅为N＋M（M为分段数目，1≤M≤N），同时排序速度明显优于Quick Sort、分段快速排序、分“档”统计插入排序和Proponion Split Sort等算法。     

基于DDS和DSP的GMSK调制算法分析

提出一种基于直接数字式频率合成器（DDS）和数字信号处理（DSP）的高斯滤波最小频移键控（GMSK）调制算法，该算法具有实现简单，波形准确等特点，适用于低功耗的无线通信系统，详细介绍了GMSK调制原理，以及基于DDS和DSP的调制算法，并对该算法的性能进行了仿真和测试分析。     

基于DDS和DQUC的宽带多普勒频率模拟器的设计

介绍了直接数字频率合成（DDS）和直接正交上变频（DQUC）的基本原理，提出了基于DDS和DQUC的宽带多普勒频率模拟器设计方案，该方案在微波频段保持了DDS的所有优点，并抑制了在混频器中上变频时双边带中的无用边带。最后，介绍了基于AD9854和AD8346的直接正交上变频器优化设计的具体措施。并给出了实验结果。     

一类新型混沌密码序列的理论设计

作者提出了“分段二次非线性映射”。该映射可产生具有均匀分布函数和δ-like自相关函数的混沌序列。与“逐段线性”映射相比,该新映射提供了更强的安全性。     

四象限探测器用于激光跟踪仪目标脱靶量测量

介绍了基于四象限探测器的激光跟踪仪目标脱靶量测量系统。根据四象限探测器的工作原理和跟踪激光的光斑特性,分析得出目标脱靶量与四象限探测器输出电流信号的关系为非线性。针对非线性关系不易快速解算的难题,文中采用了分段线性插值算法。使用高精度位移平台对测量系统进行标定并开展了测量实验。结果表明,该系统测量速度快,每秒测量次数可达600次以上;测量精度高,在±500μm量程范围内测量精度可达5μm。该系统可以广泛应用于需要微小位移测量的相关领域。     

使用较少FPGA资源实现DDS的方法

文章提出一种采用数字坐标旋转（CORDIC）算法实时计算正弦值的方法，替代传统的DDS采用的正弦查找表，显著地节省了FPGA的内部资源，极大的提高了DDS的频率和相位分辨率，从而扩展DDS技术的应用范围；同时，分析该方案实现中可能存在的问题，并给出解决方案。     

一种基于DT分割及自适应DCT的图像编码方法

提出了一种结合ＤＴ（Ｄｅｌａｕｎａｙ Ｔｒｉａｎｇｕｌａｔｉｏｎ）分割及任意形状自适应ＤＣＴ（ＳＡＤＣＴ）的图像编码方法。使用基于图像内容的ＤＴ分割及ＤＴ内的线性插值来逼近原始图像,然后在每一ＤＴ三角形内使用ＤＣＴ变换来编码逼近误差。模拟结果表明：与传统的ＤＣＴ方法相比,这种编码方法明显改善了恢复图像的质量     

Theoretical Upperbound of the Spurious-Free Dynamic Range in Direct Digital Frequency Synthesizers Realized by Polynomial Interpolation Methods

In this paper, a universal mathematical method is proposed to determine the upperbound of the spurious-free dynamic range (SFDR) in direct digital frequency synthesizers (DDFSs) realized by piecewise polynomial interpolation methods. The Fourier series is used to establish a linear matrix relationship between the frequency spectrum of the interpolated sinusoidal signal and the coefficients of the interpolating polynomials. This matrix relationship can be considered as a linear overdetermined system of equations, which can be solved for the ideal spectrum where the fundamental harmonic has an amplitude of one and the other harmonics are zero. It is shown that the Moore-Penrose pseudoinverse and Chebyshev minimax methods find the coefficients corresponding to the largest signal-to-noise ratio and maximum SFDR designs, respectively. The proposed method is used to show that the maximum SFDR of a DDFS based on the even fourth-order polynomial interpolation is 74.35 dBc. A DDFS based on the aforementioned method is designed and its architecture is optimized to obtain an SFDR of 72.2 dBc. A VLSI implementation of the proposed DDFS is also reported.     

Direct digital frequency synthesizers with polynomial hyperfolding technique

A new approach to design the phase to sine mapper of a direct digital frequency synthesizer (DDFS) is presented. The proposed technique uses an optimized polynomial expansion of sine and cosine functions to achieve either a 60-dBc spurious free dynamic range (SFDR), with a second-order polynomial, or a 80-dBc SFDR, with third-order polynomials. Polynomial computation is done by using new canonical-signed-digit (CSD) hyperfolding technique. This approach exploits all the symmetries of polynomials parallel computation and uses CSD encoding to minimize hardware complexity. CSD hyperfolding technique is also presented in the paper. The performances of new DDFS compares favorably with circuits designed using state-of-the-art Cordic algorithm technique.     

Low-power direct digital frequency synthesis for wirelesscommunications

A low-power direct digital frequency synthesizer (DDFS) architecture is presented. It uses a smaller lookup table for sine and cosine functions compared to already existing systems with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points. A DDFS with 60-dBc spectral purity 29-Hz frequency resolution, and 9-bit output data for sine function generation is being implemented in 0.8-μm CMOS technology. Experimental results verify that the average power dissipation of the DDFS logic is 9.5 mW (at 30 MHz, 3.3 V)     

Efficient, ROM-less DDFS using non-linear interpolation and non-linear DAC

A non-linear interpolation based ROM-less Direct Digital Frequency Synthesisiser (DDFS) is more efficient than previous systems as each current cell in a non-linear DAC is used more effectively. This was achieved by forming an analogue voltage from a small linear DAC addressed by phase bits that are usually discarded. The analogue voltage was connected to a selected current source in a thermometer decoded non-linear DAC to allow non-linear interpolation between the conventional, phase limited output levels. By increasing the number of phase bits the spurious free dynamic range (SFDR) was improved without increasing the size of the non-linear DAC. Modelling and simulation of the non-linear response of the differential switch based current cell revealed suitable parameters. The architecture of 64 current cells used a modified thermometer decoder and three-state switch in each current cell. Simulation and testing of 10 sample circuits demonstrated a robust DDFS with SFDR better than −60 dBc and suitable for use in a wide range of instrumentation systems.     

一种基于最佳平方逼近算法的数字频率综合器

提出一种基于最佳平方逼近算法的数字频率综合器的设计方法,同时采用非均匀分段纠正误差方式对输出正余弦波形进行优化。通过MATLAB系统仿真分析结果表明,采用这种新方法设计的数字频率综合器性能具有精度高、误差小和结构简单的优点,最差情况下的无杂散动态范围(SFDR)小于-80dBc。     

High-performance direct digital frequency synthesizers using piecewise-polynomial approximation

This paper presents new techniques to implement direct digital frequency synthesizers (DDFSs) with optimized piecewise-polynomial approximation. DDFS performances with piecewise-polynomial approximation are first analyzed, providing theoretical upperbounds for the spurious-free dynamic range (SFDR), the maximum absolute error, and the signal-to-noise ratio. A novel approach to evaluate, with reduced computational effort, the near optimal fixed-point coefficients which maximize the SFDR is described. Several piecewise-linear and quadratic DDFS are implemented in the paper by using novel, single-summation-tree architectures. The tradeoff between ROM and arithmetic circuits complexity is discussed, pointing out that a sensible silicon area reduction can be achieved by increasing ROM size and reducing arithmetic circuitry. The use of fixed-width arithmetic can be combined with the single-summation-tree approach to further increase performances. It is shown that piecewise-quadratic DDFSs become effective against piecewise-linear designs for an SFDR higher than 100 dBc. Third-order DDFSs are expected to give advantages for an SFDR higher than 180 dBc. The DDFS circuits proposed in this paper compare favorably with previously proposed approaches.     

一种新的正交直接数字频率合成器设计方案

为了提高正交直接频率合成器输出频谱纯度和降低逻辑单元占用率,提出了一种新的分解二阶多项式近似算法。这种算法是将正(余)弦函数分解为几个相关函数,进行二阶多项式近似。与传统二阶多项式近似算法相比,该算法输出频谱纯度较高,无杂散动态范围(SFDR)可达到99.3dBc;该算法所占用的逻辑单元比二阶多项式近似算法减少20%。实验表明,在设计高频谱性能的正交直接数字频率合成器(Quadrature-DDFS)方面,该算法具有明显优势。     

An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter

An 800-MHz low-power direct digital frequency synthesizer (DDFS) with an on-chip digital-to-analog (D/A) converter is presented. The DDFS consists of a phase accumulator, two phase-to-sine converters, and a D/A converter. The high-speed operation of the DDFS is enabled by applying parallelism to the phase-to-sine converter and by including a D/A converter in a single chip. The on-chip D/A converter saves delay and power consumption due to interchip interconnections. The DDFS considerably reduces power consumption by using several low-power techniques. The pipelined parallel accumulator consumes only 22% power of a conventional pipelined accumulator with the same throughput. The quad line approximation (QLA) and the quantization and error ROM (QE-ROM) minimize the ROM to generate a sine wave. The QLA saves 4 bits of the sine amplitude by approximating the sine function with four lines. The QE-ROM quantizes the ROM data by magnitude and address and then it stores the quantized values and the quantization errors separately. The ROM size for a 9-bit sine output is only 368 bits. A DDFS chip is fabricated in a 0.35-/spl mu/m CMOS process. It consumes only 174 mW at 800 MHz with 3.3 V. The chip core area is 1.47 mm/sup 2/. The spurious-free dynamic range (SFDR) is 55 dBc.