Fluid flow phenomena in the electromagnetic stirring of continuous casting systems,part 1: the behaviour of a cylindrically shaped laboratory scale installation

A model is developed to calculate the flow field produced by electromagnetic stirring generated by a rotating magnetic field. This study has considerable importance due to its applicability to continuous casting systems. Three cases are considered, the first, in which steady continuous stirring is studied, and the numerical results are found to agree well with the experimental observations by other workers. In the second case, alternating stirring is examined, and the critical role of switching frequencies is discussed. Finally, a preliminary allowance is made for free surface deformation for the continuous stirring situation. The effective viscosity is deduced from the transport equations for K, the turbulence kinetic energy, and for ?, the rate of viscous dissipation. The transport equation for K is modified to account for turbulence enhancement due to electromagnetic effects.     

Built-in self-testing of random-access memories

Built-in self-test (BIST) methods are examined, including the fault models and the test algorithms on which the BIST implementations are based. The notion of generic test architectures suitable for implementing a wide variety of test algorithms is introduced. A taxonomy for test architectures is provided and used to categorize BIST implementations, and important implementations are surveyed. It is demonstrated that BIST is a viable solution to the problem of testing large memories and that approaches based on test architectures rather than on test algorithms are more versatile and will likely predominate in the future     

A brief review of models for computing solar radiation on inclined surfaces

Modelling of solar energy systems requires estimation of the hourly radiation incident on surfaces of different tilts and orientations. Most meteorological stations report radiation values on a daily rather than hourly basis. Again, the value of the diffuse component may or may not be reported. Hence, different strategies may be encountered, for each location, with the common goal of computing hourly radiation on inclined surfaces.

In this study, five different schemes are presented to achieve this goal. In each scheme, certain correlations are required which are discussed in detail. The study is divided into five sections, each dealing with a specific type of correlation. These sections are: (i) correlations between daily diffuse and global radiation; (ii) correlations between hourly/daily global radiation; (iii) correlations between hourly/daily diffuse radiation; (iv) correlations between hourly diffuse and global radiation; and (v) models for computing diffuse sky radiation on inclined surfaces. The last section deals extensively with the anisotropic nature of sky diffuse radiation.

The important aspects of all correlation studies are highlighted, and the relative merits and demerits of their results are brought to light.

Mathematical expressions, where available, for models/correlations are provided so that the reader will have access to a comprehensive study. This information should be useful for modelling purposes in which computation of radiation on surfaces of different orientations and tilts is required.     

Analysis and test procedures for NOR flash memory defects

Widespread use of non-volatile memories, especially flash memories, in diverse applications such as in mobile computing and system-on-chip is becoming a common place. As a result, testing them for faults and reliability is drawing considerable interest of designers and researchers. One of the most predominant failure modes for which these memories must be tested is called disturb faults. In this paper, we first analyze different defects that are responsible for disturb faults using a 2-dimension device simulator. We determine the impact of various defects on cell performance and develop a methodology based on channel erase technique to detect these defects. Our tests are efficient and can be converted to march tests prevalently used to test memories. We also propose a very low cost design-for-testability approach that can be used to apply the test technique developed in this paper.     

Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester

Numerous solutions have been proposed to reduce test data volume and test application time during manufacturing testing of digital devices. However, time to market challenge also requires a very efficient debug phase. Error identification in the test responses can become impractically slow in the debug phase due to large debug data, slow tester speed, and limited memory of the tester. In this paper, we investigate the problems and solutions related to using a relatively slow and limited memory tester to observe the at-speed behavior of fast circuits. Our method can identify all errors in at-speed scan BIST environment without any aliasing and using only little extra overhead by way of a multiplexer and masking circuit for diagnosis. Our solution takes into account the relatively slower speed of the tester and the reload time of the expected data to the tester memory due to limited tester memory while reducing the test/debug cost. Experimental results show that the test application time by our method can be reduced by a factor of 10 with very little hardware overhead to achieve such advantage.     

Verification of wind resource study of a Scottish region

In a survey of the practical wind energy resource present in the Tayside Region of Scotland it was estimated that over 1500 km² of land is suitable for wind energy development in the Region after consideration of a range of physical, technical and institutional factors. Wind speed data for this survey was obtained from the Energy Technology Support Unit (ETSU) UK Wind Speed Data Package. To verify the wind speeds obtained from the ETSU package a representative sample of sites in and around the identified areas of potential in Tayside were modelled for mean annual wind speed using the Wind Atlas Analysis and Application Program (WA^sP). The wind speeds for the sites obtained from the WA^sP analysis were compared with those obtained from the ETSU UK Wind Speed Data Package and conclusions drawn as to the reliability of the Tayside wind energy survey and the general applicability of the ETSU package for broad wind energy resource assessment.     

Stimulation of pancreatic growth by cholecystokinin is mediated by high affinity receptors on rat pancreatic acinar cells

Pancreatic acinar cells possess both high low affinity receptors for cholecystokinin. The cholecystokinin analog caerulein, which exerts a trophic effect on the rat pancreas, acts as an agonist at both types of receptors. In contrast, the synthetic analog CCK-JMV-180, which also acts as an agonist at high affinity receptors, opposes the action of caerulein on the low affinity receptors. We report that infusion of either caerulein or CCK-JMV-180 into rats increases [3H]-thymidine incorporation into pancreatic DNA and causes the pancreatic weight as well as content of DNA, RNA, and protein to increase. CCK-JMV-180 also stimulates in-vitro incorporation of [3H]-thymidine into DNA of cultured rat acini. The finding that both caerulein and CCK-JMV-180 exert the same trophic effect on pancreatic acinar cells indicates that this effect is mediated via high affinity acinar cell cholecystokinin receptors.     

A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging

Temporal unreliability due to aging, such as Negative-Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) effects etc., in the CMOS circuits may not appear just after the chip production, instead it becomes apparent when it is used under certain workload and environmental conditions over time. Identifying aged paths that may become critical to circuit performance, is a real challenge for many researchers and reliability engineers. In this work, firstly we identify a set of parameters that impact the circuit performance under aging and use them in the proposed algorithm which is substantially faster than commercially available SPICE simulator with an approx 94% accuracy in estimating path delays. Secondly, we explore the possibility of using the proposed methodology, instead of using time expensive SPICE and pessimistic static timing analysis (STA), to identify a set of speed-limiting paths under aging. Experimental results demonstrate the effectiveness of the proposed algorithm and the associated methodology in comparison to SPICE simulated results.     

Simulating program disturb faults in flash memories using SPICE compatible electrical model

Electrical simulation is an important tool that enables designers to evaluate different design alternatives and assess their performance. In memory technology, these tools are used to study the performance of different cell structures and implementations. In this paper we use such simulations to study the impact of defects on the performance of flash memory bitcells. In particular, using a device level simulator, we develop a SPICE compatible model to simulate the operation of a 1T flash bitcell. We then describe a fault injection technique that can be used, in conjunction with the model, to simulate faulty cell behavior. The model is used to simulate different defects in the oxide layer of the flash core memory element. The impact of defects on bitcell behavior under disturb and normal operations is investigated and evaluated. The model is demonstrated to be valuable to evaluate the appropriateness of the logic tests and stress tests used to detect such defects in flash memories.     

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing

At-speed scan testing, based on ATPG and ATE, is indispensable to guarantee timing-related test quality in the DSM era. However, at-speed scan testing may incur yield loss due to excessive IR-drop caused by high test (shift & capture) switching activity. This paper discusses the mechanism of circuit malfunction due to IR-drop, and summarizes general approaches to reducing switching activity, by which highlights the problem of current solutions, i.e. only reducing switching activity for one capture while the widely used at-speed scan testing based on the launch-off-capture scheme uses two captures. This paper then proposes a novel X-filling method, called double-capture (DC) X-filling, for generating test vectors with low and balanced capture switching activity for two captures. Applicable to dynamic & static compaction in any ATPG system, DC X-filling can reduce IR-drop, and thus yield loss, without any circuit/clock modification, timing/circuit overhead, fault coverage loss, and additional design effort.