Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy

This paper discusses an automated method to divide scan chains into multiple scan segments that are suitable for power-constrained at-speed testing using the skewed-load test application strategy. By dividing a circuit into multiple partitions, which can be tested independently, both power during shift and power during capture can be controlled. Despite activating one partition at a time, we show how through conscious construction of scan segments, high transition fault coverage can be achieved, while reducing test time of the circuit and employing third party test generation tools.

A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment

A new scan architecture for both low power testing and test volume compression is proposed. For low power test requirements, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the distribution of unspecified bits in the test cubes. In order to optimize the proposed process, a novel graph-based heuristic is proposed to partition the scan chains into several segments. For test volume reduction, a new LFSR reseeding based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, s _max, virtually. The performance of a conventional LFSR reseeding scheme highly depends on s _max. In this paper, by using different clock phases between an LFSR and scan chains, and grouping the scan cells by a graph-based grouping heuristic, s _max could be virtually reduced. In addition, the reduced scan rippling in the proposed test compression scheme can contribute to reduce the test power consumption, while the reuse of some test results as the subsequent test stimulus in the low power testing scheme can reduce the test volume size. Experimental results on the largest ISCAS89 benchmark circuits show that the proposed technique can significantly reduce both the average switching activity and the peak switching activity, and can aggressively reduce the volume of the test data, with little area overhead, compared to the previous methods.

Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing

In this paper we propose a new approach to generate a primary input blocking pattern for applying to the primary inputs during shift cycle such that the switching activity occurred in the combinational part of the circuit under test can be suppressed as much as possible. The primary input blocking technique suppresses transitions of gates in the combinational part during scan by assigning controlling values to one of the gates' inputs. However, simultaneously assigning controlling values to the gates may result in conflicts in the setting of binary values on the primary inputs. Instead of the heuristics based on fanout in other approaches, we use the impact function which is based on transition density to determine the priorities of the gates to be blocked. Experiments performed on the ISCAS 89 benchmark circuits show that the proposed approach can always produce better results than the existing approaches.

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique

With increasing defect density and process variations in nanometer technologies, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. This paper presents a novel test technique based on supply gating, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overhead. Experimental results on a set of ISCAS89 benchmarks show an average reduction of 34% in area overhead with an average improvement of 65% in delay overhead and 90% in power overhead during normal mode of operation, compared to the enhanced scan implementation.

Controllability of Static CMOS Circuits for Timing Characterization

Timing violations, also known as delay faults, are a major source of defective silicon in modern Integrated Circuits (ICs), designed in Deep Sub-micron (DSM) technologies, making it imperative to perform delay fault testing in these ICs. However, DSM ICs, also suffer from limited controllability and observability, which impedes easy and efficient testing for such ICs. In this paper, we present a novel Design for Testability (DFT) scheme to enhance controllability for delay fault testing. Existing DFT techniques for delay fault testing either have very high overhead, or increase the complexity of test generation significantly. The DFT technique presented in this paper, exploits the characteristics of CMOS circuit family and reduces the problem of delay fault testing of scan based sequential static CMOS circuits to delay fault testing of combinational circuits with complete access to all inputs. The scheme has low overhead, and also provides significant reduction in power dissipation during scan operation.

Low-Power FPGA-Implementation of <Emphasis Type="Italic">atan</Emphasis>(<Emphasis Type="Italic">Y</Emphasis>/<Emphasis Type="Italic">X</Emphasis>) Using Look-Up Table Methods for Communication Applications

This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. The architecture takes advantage of embedded hard-cores of the FPGA device to achieve lower power consumption with respect to an atan(Y/X) operator based on CORDIC algorithm or conventional LUT-based methods. The proposed architecture can compute the atan(Y/X) with a latency of two clock cycles and its power consumption is 49% lower than a CORDIC or 46% lower than multipartite approach.

Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells

In this paper, we show that not every scan cell contributes equally to the power consumption during scan-based test. The transitions at some scan cells cause more toggles at the internal signal lines of a circuit than the transitions at other scan cells. Hence the transitions at these scan cells have a larger impact on the power consumption during test application. We call these scan cells power sensitive scan cells. A signal probability based approach is proposed to identify a set of power sensitive scan cells. Additional hardware is added to freeze the outputs of power sensitive scan cells during scan shifting in order to reduce the shift power consumption. Experimental results on industrial circuits show that on average more than 45% of the scan shift power can be eliminated when freezing only 5% of power sensitive scan cells.

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction

Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, we propose in this paper to modify an existing test data compression technique (Wang Z, Chakrabarty K in Test data compression for IP embedded cores using selective encoding of scan slices. IEEE International Test Conference, paper 24.3, 2005) so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded Intellectual Property (IP) cores. Compared to the initial solution that fill don’t-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS’89 and ITC’99 benchmark circuits and on a number of industrial circuits. Results show that up to 14× reduction in test data volume and 98% test power reduction can be obtained simultaneously.

RF Testing on a Mixed Signal Tester

In this paper, testing of radio frequency (RF) devices with mixed-signal testers is discussed. General purpose automatic test equipment (ATE) will be used. In this paper, a more universal test structure utilizing RF building blocks is proposed. A global positioning system (GPS) device is used as an example to illustrate how to develop the RF test plan with this usage. The test plan developed includes fast, cost-effective and dedicated circuitry.

A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines

Interconnection opens have become important defects in nanometer technologies. The behavior of these defects depends on the structure of the affected devices, the trapped gate charge and the surrounding circuitry. This work proposes an enhanced test generation methodology to improve the detectability of interconnection opens. This test methodology is called OPVEG. OPVEG uses layout information and a commercial stuck-at ATPG. Those signal values at the coupled lines which favor the detection of the opens, under a boolean based test, are attempted to be generated. The methodology is applied to four ISCAS85 benchmark circuits. The results show that a significant number of considered coupled signals are set to proper logic values. Hence, the likelihood of detection of interconnection opens is increased. The results are also given in terms of the amount of coupling capacitance having logic conditions favoring the defect detection. This shows the OPVEG benefits. Furthermore, those lines difficult to test can be identified. This information can be used by the designer to take design for test measures.

Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits

Due to the absence of a global clock and the presence of more state holding elements that synchronize the control and data paths, conventional Automatic Test Pattern Generation (ATPG) algorithms fail when applied to asynchronous circuits, leading to poor fault coverage. This paper presents a design for test (DFT) technique for a popular asynchronous design paradigm called NULL Convention Logic (NCL) aimed at making NCL designs testable using existing DFT tools with reasonable gate overhead. The proposed technique performs test points (TPs) insertion using Sandia Controllability and Observability Program (SCOAP) analysis to enhance the controllability of feedback nets and observability for fault sites that are flagged unobservable. An Automatic DFT Insertion Flow (ADIF) algorithm and a custom ATPG NCL primitive gates library are developed. The developed DFT technique has been verified on several NCL benchmark circuits

LPTest: a Flexible Low-Power Test Pattern Generator

This paper presents a low power test pattern generator, LPTest, that minimizes the peak power consumption during the shift and capture cycles for scan-based stuck-at and transition fault testing. LPTest incorporates both power-aware ATPG and low-power X-filling techniques to achieve higher power reduction. Its enabling technique is a power estimation method which assesses the lower-bounds of the shift-in, shift-out, and capture powers of a partially specified test pattern. The lower-bound estimation method is utilized in LPTest’s ATPG engine, dynamic compaction, and X-filling. LPTest has been validated using ISCAS89 benchmark circuits. When considering all cycles, LPTest achieves better than 22% peak WSA (weighted switching activity) reduction for stuck-at and transition faults compared to a commercial ATPG with high merge ratio and random-fill options. Meanwhile, the average power reduction is better than 43%. When only capture power is of concern, LPTest attains more than 46% WSA reduction for stuck-at and transitions.     

Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding

This paper proposes a class of test compression for IP (intellectual property) core testing. The proposed compression requires only test cubes for the IP cores and it dose not require the structural information about the IP cores. It uses both a reconfigurable network and classes of coding, namely fixing-flipping coding and fixing-shifting-flipping coding. The proposed compression is evaluated from the viewpoint of compression rates and hardware overhead. For three out of four large ISCAS89 benchmark circuits, the compression rates of the proposed compression are better than those of the four existing test compressions.

Isolation of Failing Scan Cells through Convolutional Test Response Compaction

This paper describes a non-recursive fault diagnosis technique for scan-based designs with convolutional test response compaction. The proposed approach allows a time-efficient and accurate identification of failing scan cells using Gauss–Jordan elimination method.

A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters

Testing high-speed A/D converters for dynamic specifications needs test equipment running at high frequency. In this paper, a methodology to test high-speed A/D converters using low-frequency resources is described. It is based on the alternate testing approach. In the proposed methodology, models are built to map the signatures of an initial set of devices, obtained on the proposed low-cost test set-up, to the dynamic specifications of the same devices, obtained using high-precision test equipment. During production testing, the devices are tested on the low-cost test set-up. The dynamic specifications of the devices are estimated by capturing their signatures on the low cost test set-up and processing them with the pre-developed models. As opposed to the conventional method of dynamic specification testing of data converters, the proposed approach does not require the tester resources running at a frequency higher than the device-under-test (DUT). The test methodology was verified in simulations as well as in hardware with specification estimation error of less than 5%.

Online Testing of MEMS Based on Encoded Stimulus Superposition

This article presents a technique that enables online testing of sensors through the superposition of the test stimulus onto the measurand. Perturbations due to the surrounding environment can very often introduce fluctuations in the test output creating a major concern for this type of sensor testing. In this paper, a signal processing technique is proposed where the test stimulus is encoded by a pseudo-random sequence in order to reduce the test output fluctuations. The trade-off between the level of rejection of a perturbation and the overall test time is studied. In the case of the MEMS accelerometer considered in this paper, it is theoretically demonstrated that the rejection is more than 20 dB for a test time of 2.55 s. Furthermore, excessively strong perturbations can be monitored so that the test status is updated only if the accuracy of the test signal permits so. The technique has been implemented on a demonstration board and validated on a vibration platform.

Finite-state Markov Model for Lognormal,Chi-square (Central), Chi-square (Non-central), and <Emphasis Type="Italic">K</Emphasis>-distributions

This paper formulates a finite-state Markov channel model to represent received signal-to-noise (SNR) ratios having lognormal, K-distribution, chi-square (central) and chi-square (non-central) distributions in a slow fading channel. The range of the SNRs is partitioned into a finite number of states following earlier works in literature. Performance measures like level crossing rates, steady-state probabilities, transition probabilities, and state-time durations are derived, and numerical results are plotted and discussed for the FSMC models for all the distributions.

Securing Scan Control in Crypto Chips

The design of secure ICs requires fulfilling means conforming to many design rules in order to protect access to secret data. On the other hand, designers of secure chips cannot neglect the testability of their chip since high quality production testing is primordial to a good level of security. However, security requirements may be in conflict with test needs and testability improvement techniques that increase both observability and controllability. In this paper, we propose to merge security and testability requirements in a control-oriented design for security scan technique. The proposed security scan design methodology induces an adaptation of two main aspects of testability technique design: protection at protocol level and at scan path level. Without loss of generality, the proposed solution is evaluated on a simple crypto chip in terms of security and design cost.

Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates

Reversible logic design is a well-known paradigm in digital computation. In this paper, quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic in array systems. Testability of 1D arrays consisting of reversible QCA gates is investigated for multiple faulty modules. It has been shown that fault masking is possible in the presence of multiple faults without additional lines for controllability and observability. A technique for achieving C-testability of a 1D array is introduced by adding lines for observability. By adding lines for controllability, as well as observability, the array may be fully tested with a smaller number of test patterns. Different cases of arrays made of QCA reversible gates are presented to illustrate the applicability of the proposed testing method.

Optimizing complexity in Benes-type WDM switching networks

In this paper, we propose a new Benes-type wavelength division multiplexing (WDM) optical network with space-wavelength switching capability. Intuitively, adding wavelength switching capability to space Benes networks requires the use of additional hardware components (i.e., wavelength converters). However, in this paper, we show that a Benes network with full-permutation capability in both space and wavelength domains can be designed using a smaller number of hardware components but the same number of stages as that in a space-only Benes network. In addition, wavelength conversion in the proposed network occurs only between two pre-defined wavelengths, eliminating the need for any expensive wide-range wavelength converters. The proposed Benes network is based on the newly proposed concept of wavelength-exchangeable permutation networks. Wavelength-exchangeable networks implement single-step space and wavelength switching and hence reduces the number of hardware components. We show that, such wavelength-exchangeable networks possess some interesting properties that can be used for designing routing algorithms to improve signal quality.