Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing |
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Authors: | Xiaoqing Wen Kohei Miyase Tatsuya Suzuki Seiji Kajihara Laung-Terng Wang Kewal K Saluja Kozo Kinoshita |
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Affiliation: | (1) Kyushu Institute of Technology, Kawazu 680, Iizuka Fukuoka, 820-8502, Japan;(2) Denso Techno Co., Nagoya Aichi, 450-0002, Japan;(3) SynTest Technologies, Inc., 505 S. Pastoria Avenue, Sunnyvale, CA, USA;(4) University of Wisconsin–Madison, Madison, WI 53706, USA;(5) Osaka Gakuin University, Suita Osaka, 564-8511, Japan |
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Abstract: | At-speed scan testing, based on ATPG and ATE, is indispensable to guarantee timing-related test quality in the DSM era. However,
at-speed scan testing may incur yield loss due to excessive IR-drop caused by high test (shift & capture) switching activity.
This paper discusses the mechanism of circuit malfunction due to IR-drop, and summarizes general approaches to reducing switching
activity, by which highlights the problem of current solutions, i.e. only reducing switching activity for one capture while
the widely used at-speed scan testing based on the launch-off-capture scheme uses two captures. This paper then proposes a
novel X-filling method, called double-capture (DC) X-filling, for generating test vectors with low and balanced capture switching activity for two captures. Applicable to dynamic & static
compaction in any ATPG system, DC X-filling can reduce IR-drop, and thus yield loss, without any circuit/clock modification, timing/circuit overhead, fault coverage
loss, and additional design effort.
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Keywords: | At-speed scan testing Capture switching activity X-filling Test cube ATPG Low power testing |
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