A Hybrid Fractal Metamaterial Inspired Multiband Antenna for Wireless Applications

Wireless Personal Communications - In this paper a multiband (hepta-band) antenna loaded with hybrid fractal structures and metamaterial cell (SRR/CSRR) is proposed to cover the wireless...     

Phase Diagram and Upper Critical Field of Homogeneously Disordered Epitaxial 3-Dimensional NbN Films

We report the evolution of superconducting properties with disorder, in 3-dimensional homogeneously disordered epitaxial NbN thin films. The effective disorder in NbN is controlled from moderately clean limit down to Anderson metal?Cinsulator transition by changing the deposition conditions. We propose a phase diagram for NbN in temperature-disorder plane. With increasing disorder, we observe that as k _F l??1 the superconducting transition temperature (T _c ) and normal state conductivity in the limit T??0 (?? ₀) go to zero. The phase diagram shows that in homogeneously disordered 3-D NbN films, the metal?Cinsulator transition and the superconductor?Cinsulator transition occur at a single quantum critical point, k _F l??1.     

Study of Shubnikov-de Haas oscillations and measurement of hole effective mass in compressively strained InXGa1−XSb quantum wells

In_XGa_1−XSb has the highest hole mobility amongst all III-V semiconductors which can be enhanced further with the use of strain. The use of confinement and strain in In_XGa_1−XSb quantum wells lifts the degeneracy between the light and heavy hole bands which leads to reduction in the hole effective mass in the lowest occupied band and an increase in the mobility. We present magnetotransport measurements on compressively strained In_XGa_1−XSb and GaSb quantum wells. Hall-bar and Van de Pauw structures were fabricated and Shubnikov-de Haas oscillations in the temperature range of T = 2-10 K for magnetic fields of B = 0-9 T were measured. The reduction of effective hole mass with strain was quantified. These results are in excellent agreement with modeling results from band structure calculations of the effective hole mass in the presence of strain and confinement.     

Interconnect limits on gigascale integration (GSI) in the 21stcentury

Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction. At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. At the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. At the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in size every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance. Increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node     

Rapid thermal processing uniformity using multivariable control ofa circularly symmetric 3 zone lamp

Defect introduction and process variations commonly observed in conventional rapid thermal processing (RTP) systems have impeded its widespread acceptance in manufacturing. The main problem lies in the conventional approach of using scalar control, where optimal steady-state temperature uniformity at one set of processing conditions is used to fix the hardware geometry, leaving only one input variable-the lamp power-for control. It is demonstrated that this control is inadequate, since the radiative and convective heat exchange at the wafer are functions of the processing conditions, and that the resultant nonuniformity can be corrected by dynamic control of the spatial optical flux profile. Such control is demonstrated through two key innovations: a lamp system in which tungsten-halogen point sources are configured in three concentric rings to provide a circularly symmetric flux profile, and multivariable control whereby each of the three rings is independently and dynamically controlled to provide for control over the spatial flux profile. This approach offers good temperature uniformity over transients, thus improving reliability of individual processes     

Preliminary results on a-SiC:H based thin film light emitting diode by hot wire CVD

Preliminary results on the first hot wire deposited a-SiC:H based thin film light emitting p–i–n diode having the structure glass/TCO(SnO₂:F)/p-a-SiC:H/i-SiC:H/n-a-SiC:H/Al are reported. The paper discusses the results of our attempts to optimize the p-, i- and the n-layers for the desired electrical and optical properties. The optimized p-layers have a bandgap E_g2 eV and conductivity a little lower than 10⁻⁵ (Ω cm)⁻¹. On the other hand, the optimized n-type a-SiC:H show a conductivity of 10⁻⁴ (Ω cm)⁻¹ with bandgap 2.06 eV. The highest bandgap of the intrinsic layer is approximately 3.4 eV and shows room temperature photoluminescence peak at approximately 2.21 eV. Thin film p–i–n diodes having i-layers with E_g from 2.7 to 3.4 eV show white light emission at room temperature under forward bias of >5 V. However, the 50-nm thick devices show appreciable reverse leakage current and a low emission intensity, which we attribute to the contamination across the p–i interface since these devices are made in a single chamber with the same filament.     

High-mobility low band-to-band-tunneling strained-Germanium double-gate heterostructure FETs: Simulations

Large band-to-band tunneling (BTBT) leakage currents can ultimately limit the scalability of high-mobility (small-bandgap) materials. This paper presents a novel heterostructure double-gate FET (DGFET) that can significantly reduce BTBT leakage currents while retaining its high mobility, making it suitable for scaling into the sub-20-nm regime. In particular, through one-dimensional Poisson-Schrodinger, full-band Monte Carlo, and detailed BTBT simulations, the tradeoffs between carrier transport, electrostatics, and BTBT leakage in high-mobility sub-20-nm Si-strained SiGe-Si (high germanium concentration) heterostructure PMOS DGFETs are thoroughly analyzed. The results show a dramatic (>100/spl times/) reduction in BTBT and an excellent electrostatic control of the channel while maintaining very high drive currents and switching frequencies in these nanoscale transistors.     

High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/<3 nm) very high Ge fraction (/spl sim/ 80%) channel and Si cap (T/sub Si cap/<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (T/sub SOI/=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.