RISC-V随机化过程的抗功耗分析攻击设计

提出了一种基于随机化过程来抵御功耗分析攻击的方法。该随机化过程综合采用3种手段：在指令执行过程中，随机生成并插入与上一条真实指令相似的虚拟指令，使得插入的随机功耗与上条真实指令相近以避免被准确分析功耗；在指令执行、写回阶段插入一个随机延时来混淆指令执行时间以避免被准确定位；通过4种不同频率的时钟随机切换来对系统时钟进行扰乱以混淆瞬时功耗。基于CV32E40P处理器实现了该方法并通过相关功耗分析攻击进行实验，实验结果表明得到的最高相关性系数为0.139,比原处理器低0.641,该方法大大提高了处理器的抗功耗分析攻击能力。     

基于BP神经网络的人脸识别系统研究

本文设计了一种基于BP神经网络的人脸识别系统,并对其进行了性能分析.该系统首先利用离散小波变换获取包含人脸图像大部分原始信息的低频分量,对图像数据进行降维;再由PCA算法对人脸图像进行主成分特征提取,进一步降低图像数据的处理量;最后使用经过训练后的BP神经网络对待测人脸进行分类识别.详细介绍了离散小波变换、PCA特征提取以及BP神经网络分类设计.通过系统仿真实验与分析发现:人脸特征的提取是该系统的关键;同时,由于人脸灰度信息的统计特征与有监督训练BP神经网络分类器,使该系统只在固定类别,并且光照均匀的人脸识别应用场景中具有较高的识别准确率.因此,很难在复杂环境中应用.     

基于优化环路带宽的低噪声锁相环设计

This paper describes a low-noise phase-locked loop （PLL） design method to achieve minimum jitter. Based on the phase noise properties extracted from the transistor, and the low-pass or high-pass transfer characteristics of different noise sources to the output, an optimal loop bandwidth design method, derived from a continuous-time PLL model, further improves the jitter characteristics of the PLL. The described method not only finds the optimal loop-bandwidth to minimize the overall PLL jitter, but also achieves optimal loop-bandwidth by changing the value of the resistor or charge pump current. In addition, a phase-domain behavioral model in ADS is presented for accurately predicting improved jitter performance of a PLL at system level. A prototype PLL designed in a 0.18 μm CMOS technology is used to investigate the accuracy of the theoretical predictions. The simulation shows significant performance improvement by using the proposed method. The simulated RMS and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 10.262 ps and 46.851 ps, respectively.     

空气中脉冲电压激励的表面微放电特性(英文)

The surface micro-discharge(SMD)excited by pulsed voltage in open air is experimentally studied by measuring its voltage,current,emission image,emission spectrum,and ultraviolet(UV)absorption spectrum.It is found that the SMD occurs intermittently in each cycle,and that it consists of many filaments on the surface of grounded electrode.While the applied voltage’s peak value Up increases from 1.75 kV to 7.25 kV,the discharge area keeps expanding until Up≈6 kV,when the discharge occupies all the available area.The emission spectrum of nitrogen metastable N2(C-B)and the density of ozone increase almost linearly.The ozone density decreases hyperbolically downstream of the grounded electrode due to the diffusion in open air.The characteristics of pulsed SMD are presented and analyzed as well,which may be referred by further investigations.     

一种可靠的芯片指纹PUF电路

本文引入一种可靠的芯片指纹物理不可克隆函数（Physical Unclonable Function）电路.该PUF包括基于电流饥饿型延迟单元的工艺敏感电路、时间偏差放大器、时间偏差比较器、表决机制与扩散算法五个部分.通过捕获制造工艺的偏差,每一个工艺敏感电路可以稳定产生两路具有微弱延时差的延迟信号,然后比较生成指纹ID;设计一种新型的扩散算法改善PUF的唯一性,引入时间偏差放大器与表决机制增强PUF相对于温度与电源电压变化的稳定性.文中PUF在0.18μm CMOS工艺下实现.仿真结果表明,该PUF的输出具有均匀统计分布特征,同时在温度从-40℃至100℃,电源电压从1.7V至1.9V变化条件下,其输出ID具有97.5%的稳定性.     

室内移动机器人导航系统研究与实现

实现了一种低成本高性能室内移动机器人导航系统。针对 Cartographer 算法使用激光雷达数据在室内 Long-Corridor 场景下建图的局部匹配错误导致定位不准的问题,使用扩展卡尔曼滤波融合激光雷达、里程计和惯性测量单元 3 种数据进行位姿估计,得到较为精准的定位,可有效提高建图精度;针对传统 AMCL 算法重定位耗时长的问题,采用基于扫描匹配的重定位方法,通过将当前 Scan 与 Submap 进行匹配,降低了扫描匹配方法的重定位耗时;针对 A * 全局规划算法路径搜索时间长、拐点较多的问题,提出一种改进 A * 算法,通过优化启发函数和增加拐角优化函数,缩短了算法搜索时间,同时去除了冗余拐点。结果表明,重定位耗时减少 80.43% ,改进 A * 算法搜索时间减少 22.79% 。     

一种新的2.45GHz频率综合器设计与实现

提出了一种新的基于数字FLL的高速、低功耗2.45GHz频率综合器结构,它由鉴频器、数字控制电路、电流控制振荡器组成.它采用高速鉴频器对振荡器输出信号计数实现鉴频,数字控制电路根据鉴频结果调节振荡器输出信号频率来实现输出信号频率与目标频率的锁定.高速分频器基于异步计数结构,降低了内部模块工作频率,使得系统性能稳定;数字控制电路采用逐次逼近算法,使得锁定速度快;基于差分电流饥饿延迟单元的电流控制振荡器采用电流-电容双控模式,使得输出频率调节范围宽、精度高.该电路结构简单,易于实现,版图面积为13 200μm2.在0.18μm工艺下,仿真结果显示,其锁定时间为14μs;输出频率调节范围为1~4.5GHz;输出频率锁定2.450GHz;功耗为4.622mW.     

嵌入式人脸识别系统设计与实现

本文是基于S5PV210嵌入式平台设计实现的人脸识别系统.在嵌入式设备上设计人脸识别系统不仅需要考虑识别的准确率,还需要考虑设备周围的环境变化对人脸识别的干扰.系统中采用Adaboost算法依据人眼部的haar特征检测人脸.通过LBP纹理特征提取结合SVM识别分类的方法识别人脸.经过系统测试,系统的识别率以及对光照变化的鲁棒性满足了一般的人脸识别身份认证的需求.     

基于石墨烯电极RRAM的混合型PUF指纹电路

该文提出了一种基于阻变存储器(RRAM)的混合型物理不可克隆函数(PUF)芯片指纹电路。RRAM器件采用石墨烯电极、对称山型结构实现,具有阻值分布宽、开关比大的特点;通过引入对称RRAM阻值偏差作为PUF单元的随机熵源,提升PUF的唯一性;采用RRAM不同阻态阻值放大存储PUF单元初始偏差,提升PUF的稳定性;利用RRAM循环间随机性实现指纹ID的重构,提升PUF的安全性。混合型PUF芯片指纹电路在0.35 μm CMOS工艺下设计实现。仿真结果表明,PUF输出具有良好的稳定性与唯一性,标准温度电压下片间汉明距离为49.95%,同时温度在?40 ℃～100 ℃,电源电压在4.6 V～5.4 V范围内变化时,PUF比特错误率为0。     

一种新型的物理不可克隆函数体系结构

This paper describes a new silicon physical unclonable function(PUF) architecture that can be fabricated on a standard CMOS process. Our proposed architecture is built using process sensors, difference amplifier,comparator, voting mechanism and diffusion algorithm circuit. Multiple identical process sensors are fabricated on the same chip. Due to manufacturing process variations, each sensor produces slightly different physical characteristic values that can be compared in order to create a digital identification for the chip. The diffusion algorithm circuit ensures further that the PUF based on the proposed architecture is able to effectively identify a population of ICs. We also improve the stability of PUF design with respect to temporary environmental variations like temperature and supply voltage with the introduction of difference amplifier and voting mechanism. The PUF built on the proposed architecture is fabricated in 0.18 m CMOS technology. Experimental results show that the PUF has a good output statistical characteristic of uniform distribution and a high stability of 98.1% with respect to temperature variation from –40 to 100C, and supply voltage variation from 1.7 to 1.9 V.