电源管理芯片中过热保护电路设计

利用三极管基-射极电压的负温度特性,设计了一种用于电源管理芯片中的过热保护电路.基于BCD 0.6 μm工艺库模型,采用HSPICE仿真软件进行模拟验证,结果表明:当温度超过150 ℃时,电路输出信号发生翻转,电源管理芯片停止工作;当温度降至130℃时,芯片恢复工作.在电源电压工作范围2.5～5.5 V内,过温保护阈值变化量为0.7℃,迟滞阈值变化量为0.9 ℃,迟滞范围20℃.因此,该过热保护电路具有温度灵敏度高、关闭和开启温度点受电源影响较小、电路结构简单、版图面积小和功耗低等特点,适合集成在电源管理芯片中.     

一种用于电子标签芯片的基准电压源电路

文章分析了射频电子标签芯片电源的特点,根据电源低电压和低成本要求,讨论了传统的带隙基准源和全CMOS的基准电压源电路方案,设计并实现了一种适合电子标签芯片应用的全CMOS的基准电压源电路。该电路采用SMIC 0.18μm标准CMOS工艺实现,电源电压范围为1~5 V,电源敏感度为1~3%/V,输出电压的温度特性为3~20.7 ppm/℃,符合射频电子标签的设计要求。     

一种新型低压高精度CMOS电流源

采用低压与温度成正比基准源和衬底驱动低压运算放大器电路,设计了一种新型的低压高精度CMOS电流源电路,并采用TSMC 0.25μm CMOS Spice模型进行了电源特性、温度特性及工艺偏差的仿真．在室温下,当电源电压处于1.0～1.8V时,低压电流源输出电流I_out约为12.437～12.497μA;当温度在0～47℃范围内,输出电流为12.447μA;各种工艺偏差条件下的最大绝对偏差为0.54μA,与典型工艺模型下的相对偏差为4.34%．     

PWM/PSM双模式高压异步整流BUCK电路

为了在全负载范围内取得高转换效率,提出一种根据占空比来自动实现模式跳转的脉冲宽度调制（PWM）/跨脉冲调制（PSM）双模式的低功耗、高压直流电压转换电路.它的输入电压为3～24 V,输出电压为2.5～(VIN-0.5)V.当负载电流较大时,芯片采用开关频率为1 MHz的PWM工作模式;当负载电流减小时,采用开关频率降低的PSM模式,从而保证了在全负载电流变化范围内的高转换效率.PWM到PSM模式的跳转采用简单逻辑及最小占空比电路实现,达到了模式的自动转换.电路采用CSMC公司的0.5 μm 40 V高压混合信号模型设计并完成流片加工.测试结果表明,在5 V的输出下,当输入电压到达最大值24 V时,芯片保持了55%以上的转换效率.芯片在2种模式间可以实现平稳过渡,具有良好的负载电流调整特性.     

基于SG3525实现PWM Buck三电平变换器的控制

分析了SG3525电压词节芯片实现PWM Buck三电平变换器控制的原理.基于SG3525电压调节芯片的控制方法用集成芯片代替分立元件,大大简化了电路,可以较好地解决电路的不均压问题.最后验证了采用上述控制方法来实现对输入电压为120V(90～180 V),输出为48 V/4A,开关频率50kHz的PWM Buck三电平变换器的控制是行之有效的.     

非线性补偿的低温漂低功耗CMOS带隙基准源的设计

设计了一种基于电流模式的具有非线性补偿的低温漂低功耗带隙基准电压源,在传统电路的基础上增加一个三极管和两个电阻达到对双极型晶体管的发射结电压VBE中与温度相关的非线性项的补偿。电路采用CSMC0.5μmDPTM CMOS工艺制造。该电路结构简单,在室温下的输出电压为1.217V,在?40℃～125℃的范围内温度系数为4.6ppm/,℃在2.6～4V之间的电源调整率为1.6mV/V。在3.3V的电源电压下整个电路的功耗仅为0.21mW。     

高性能分段温度曲率补偿基准电压源设计

针对带隙基准电压源温漂高、电源抑制比(PSRR)低的问题,提出一种新颖的分段曲率补偿技术.该电路将基准源工作的全温度范围划分为3个区间,对各段温度区间进行不同的温度补偿,同时引入电流环负反馈结构,提高电路在低频时的电源抑制比,实现在-40～150℃内,温度系数为1.24×10-6,在DC时电源抑制比为-137dB.该电路采用TSMC0.6μmBCD工艺设计实现,芯片面积为0.5mm2,关断电流小于0.1μA,工作静态功耗为125μW.投片测试结果验证了电路设计的正确性,当电源电压为2.5～6.0V时,该基准源输出电压摆幅仅为0.220mV.     

一种带有温度补偿电路的射频功率放大器

针对无线通信应用的射频功率放大器,提出了一种新颖的温度补偿电路。应用该温度补偿电路,设计了一款基于InGaP/GaAs HBT工艺的两级F类功率放大器。该功率放大器采用了带温度补偿特性的有源偏置电路,能有效地提高线性度,补偿温度引起的性能偏差;输出匹配网络采用F类功率放大器谐波理论而设计。在1 920～1 980 MHz频段和电源电压3.4 V条件下,测得常温状态该功率放大器增益为27 dB;输出功率在28 dBm时功率附加效率达到42%,邻信道功率比为-36 dBc;在-20 ℃～80 ℃之间功率附加效率和邻信道功率比基本不变。     

基于CPLD的多路温度数据采集系统的设计

提出了一种基于CPLD的温度数据采集系统的设计方案,介绍了系统软硬件、外围电路,芯片间电路连接和程序的设计方法,实现了温度信号采集、A/D转换、数据运算处理和控制数码管显示输出.仿真结果表明,本系统可将温度通过电压转换为可读的数字量,并且精度达到±0.5℃,能够满足15～50℃的一般温度采集要求.     

基于ADN8810和ADN8835的混沌激光器驱动及温控电路设计

为获得对混沌激光器的高稳定性驱动电流,实现对混沌激光器驱动电流与温度的高精度调节,基于ADN8810和ADN8835芯片设计一种混沌激光器驱动及温控电路.电路可输出驱动电流0～80 m A,满足最小调节精度0. 01 m A线性可调的驱动能力;可在0. 5～4. 5 V调节半导体制冷器(thermoelectric cooler,TEC)端最大电压值以适应具有不同TEC的激光器;在0. 5～4. 3 A调节TEC最大电流值以保护激光器.实验结果证明,本电路输出的驱动电流稳定度优于0. 007%,2 h内激光器的温度最大波动为0. 17℃.能够满足混沌激光器的需求.     

Curvature Compensated CMOS Bandgap Reference with Novel Process Variation Calibration Technique

A lowtemperature coefficient( TC) bandgap reference( BGR) with novel process variation calibration technique is proposed in this paper. This proposed calibration technique compensating both TC and output value of BGR achieves fine adjustment step towards the reference voltage,while keeping optimal TC by utilizing large resistance to help layout match. The high-order curvature compensation realized by poly and p-diffusion resistors is introduced into the design to guarantee the temperature characteristic. Implemented in 180 nm technology,the proposed BGR has been simulated to have a power supply rejection ratio( PSRR) of 91 dB@100 Hz. The calibration technique covers output voltage scope of 0. 49 V-0. 56 Vwith TC of 9. 45 × 10~(-6)/℃-9. 56 × 10~(-6)/℃ over the temperature range of-40 ℃-120 ℃. The designed BGR provides a reference voltage of 500 mV,with measured TC of 10. 1 × 10~(-6)/℃.     

High voltage detection circuit for power over the ethernet

A novel high voltage detection circuit with a high accuracy and low temperature coefficient for Power over the Ethernet (PoE) application is presented. The proposed detection circuit uses a bandgap comparator to detect the input voltage without an extra comparator and a voltage reference circuit, which reduces the chip area and detection time. In order to overcome the effect of the Ethernet resistor and avoid the circulating change of the detection circuit between the detection state and classification state, the proposed circuit uses a feedback circuit to realize the hysteresis function. The proposed detection circuit is implemented in 0.5μm65 V BCD process which occupies an active area of 590μm×310 μm. The measured results show that the temperature coefficient of the threshold voltage is 26.5×10^-6／℃ over the temperature range of -40℃ to 125℃. According to the measured results of 20 chips, the average value of the threshold voltage is 11.9V±0.25V, with a standard deviation of 0.138V.     

提高SRAM PUFs密钥生成可靠性的方法

在基于PUFs的密钥生成与存储系统中,密钥生成的可靠性由PUFs响应的错误率决定.通过对不同长度下的SRAM PUFs响应进行最大错误率统计和最小熵统计发现,SRAM PUFs内部错误分布不均,导致难以选择合适的纠错码;提出使用地址块选择算法来选取错误率低的地址块,降低SRAM PUFs响应错误率,使用参数化的辅助数据算法（HDA）提高纠错能力.实验结果表明,当SRAM PUFs最大错误率为15%时,通过改变参数寄存器的长度,纠错模块可以降低11%的错误率,有效提高密钥生成的可靠性.     

恒流LDO型白光LED驱动芯片的设计研究

完成了一种具有极低脱落电压(LDO)的白光LED恒流驱动芯片的设计．利用一级温度补偿和二次比例电阻分压技术在内部集成了0.75V带隙基准源,可在2.7V到7.0V的工作电压范围内提供350mA的恒定驱动电流．当环境温度从-10℃到100℃变化时,驱动电流变化小于5.06%;电源电压有±10%跳变的情况下,驱动电流变化小于±0.8%;最小脱落电压可达120mV;控制电路功耗小于1.75mW,整个电路转换效率可达75%．     

Design of an 8 bit differential paired eFuse OTP memory IP reducing sensing resistance

For the conventional single-ended eFuse cell, sensing failures can occur due to a variation of a post-program eFuse resistance during the data retention time and a relatively high program resistance of several kilo ohms. A differential paired eFuse cell is designed which is about half the size smaller in sensing resistance of a programmed eFuse link than the conventional single-ended eFuse cell. Also, a sensing circuit of sense amplifier is proposed, based on D flip-flop structure to implement a simple sensing circuit. Furthermore, a sensing margin test circuit is proposed with variable pull-up loads out of consideration for resistance variation of a programmed eFuse. When an 8 bit eFuse OTP IP is designed with 0.18 μm standard CMOS logic of TSMC, the layout dimensions are 229.04 μm × 100.15 μm. All the chips function successfully when 20 test chips are tested with a program voltage of 4.2 V.     

低导通电阻沟槽栅极LIGBT的模拟研究

横向绝缘栅双极晶体管(LIGBT)采用少数载流子的注入来降低导通电阻,完成了5μm外延层上普通LIGBT(C-LIGBT)、3μm外延层上的Trench Gate LIGBT(TG-LIGBT)设计及仿真.研究了利用沟槽结构改善LIGBT的正向特性和利用RESURF技术改善TG-LIGBT的反向特性.通过Silvaco TCAD软件验证了了击穿电压大于500 V的两种结构LIGBT设计,实现了导通压降为1.0 V,薄外延层上小元胞尺寸,且有低导通电阻、大饱和电流的TG-LIGBT器件.     

Design of a low temperature coefficient bandgap reference with a wide temperature range

In order to meet the requirements of different applications and markets for the accuracy and reliability of IoT chips,a low temperature coefficient bandgap reference with a wide temperature range is proposed.On the basis of the traditional Banba bandgap reference structure,the circuit utilizes high-order temperature compensation technology and piecewise temperature compensation technology to improve the curvature of the output reference voltage.The temperature coefficient of the circuit is reduced.At the same time,the operating temperature range of the circuit is extended.The circuit performances are verified in the TSMC 180 nm CMOS process.Test results show that the temperature coefficient of the circuit is as low as 7.2×10^-6/℃ in the range of-40 ℃ to 160 ℃.The power supply rejection ratio at a low frequency is -48.52 dB.The static current under the 1.8 V power supply voltage is 68.38 μA,and the core area of the chip is 0.025 mm².     

3MHZ场效应管温度补偿晶体振荡器的研制

本文介绍了一种3MH_z场效应管温度补偿晶体振荡器。环境温度在-55℃～+55℃间急剧变化时,其频率稳定度≤5×10(~-7)。器件外围体积为50×48×20mm~3,功耗约为25mW输出电压0.3V(有效值)。     

Low-offset high-PSRR bandgap voltage reference

Based on the problem that the accuracy of the bandgap affects the performance of the integrated circuit, a novel BGR (bandgap voltage reference) is proposed. It utilizes a feedback compensation network to enhance PSRR and reduce the offset voltage, which improves the system stability and precision. Cadence spectre simulation has been done by the SMIC 018μm 1.8V CMOS process for validation. The results show that the achieved temperature coefficient is 34.6×10^-6/℃ over -30℃ to 100℃ and that the PSRR is -63.5dB at a low frequency. The power assumption is only 1.5μW. The circuit is suitable for a low-voltage low-power energy harvesting system.