Carrier leakage and I/Q mismatch calibrated technique

The carrier leakage and I/Q mismatch calibrated technique based on the digital baseband for the direct conversion transmitter is described. The proposed technique only needs a calibration chain to detect mismatches, and then transmits them to the digital baseband, which completes the calibrated task. The proposed method is very simple in reducing die areas and power dissipation. Under TSMC 013μm CMOS technology simulation, the calibrated error of carrier leakage is less than 15％ and the error of I/Q mismatch is less than 65％．The measurement results indicate that I/Q amplitude mismatch is reflected at twice the input frequency. The calibrated chain gain range is 15dB with a 5dB step, and the bandwidth is 20MHz.     

A programmable gain amplifier with a DC offset calibration loop for a directconversion WLAN transceiver

A high-linearity PGA(programmable gain amplifier) with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA(RXPGA) provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA(TXPGA) covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA (I and Q path) under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC(DC offset cancellation) circuit shows 10 kHz of HPCF(high pass cutoff frequency) and the DCOC settling time is less than 0.45μs.     

A 200 mA CMOS low-dropout regulator with double frequency compensation techniques for SoC applications

This paper presents a 200mA low-dropout (LDO) linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier using common source stage with variable load, which is controlled by output current, is served as the second stage for stable frequency responses. Another technique is the LDO uses pole-zero tracking compensation technique at error amplifier to achieve good frequency response. The proposed circuit was fabricated and tested in HJTC 0.18μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8V-5V and provides up to 200mA load current for an output voltage of 1.8V. The total error of the output voltage due to line and load variation is less than 0.015%. The LDO die area is 630*550μm² and the quiescent current is 130μA.     

直接变频接收机直流失调消除技术

基于传统的负反馈结构,提出一种改进的直流失调消除技术。分别采用密勒效应和线性区工作的MOS管,实现等效大电容和大电阻。采用此方法的失调消除技术易于实现片内集成。同时,使用补偿电路减小直流失调消除环路中高通截止频率随温度和工艺的变化。设计的电路高通截止频率为500Hz,芯片尺寸为740μm×780μm。     

一种应用于IEEE 802.11 b/g/n无线局域网收发机的CMOS模拟基带电路

本文提出了一种应用于直接变频无线局域网收发机的模拟基带电路,该电路采用标准的0.13微米CMOS工艺实现,包括了采用有源RC方式实现的接收4阶椭圆低通滤波器、发射3阶切比雪夫低通滤波器、包含直流失调消除伺服环路的接收可变增益放大器及片上输出缓冲器。芯片面积共1.26平方毫米。接收基带链路增益可在-11dB至49dB间以2dB步长调节。相应地,基带接收输入等效噪声电压（IRN）在50 nV/sqrt(Hz) 至30.2 nV/ sqrt(Hz)间变化而带内输入三阶交调（IIP3）在21dBm至-41dBm间变化。接收及发射低通滤波器的转折频率可在5MHz、10MHz及20MHz之间选择以符合包含802.11b/g/n的多种标准的要求。接收基带I、Q两路的增益可在-1.6dB至0.9dB之间以0.1dB的步长分别调节以实现发射IQ增益失调校正。通过采用基于相同积分器的椭圆滤波器综合技术及作用于电容阵列的全局补偿技术,接收滤波器的功耗显著降低。工作于1.2V电源电压时,整个芯片的基带接收及发射链路分别消耗26.8mA及8mA电流。     

应用于GPS接收机的宽动态范围连续VGA

针对全球定位系统(GPS)接收机中宽动态范围的要求,提出了一种伪指数近似可变增益放大器(VGA)。该VGA在改进的吉尔伯特单元基础上,采用电压-电流转换电路构成伪指数函数,通过两级级联方式来实现宽线性增益范围,且电路结构对温度不敏感。测试结果表明,当控制电压在0.4~1.45 V变化时,该VGA的线性增益范围为20~80 dB。在50 dB线性增益范围内,增益随温度变化的最大偏差不大于±1.5 dB。     

A high-performance low-power CMOS AGC for GPS application

In this paper, a wide tuning range, low power CMOS automatic gain control (AGC) with a simple architecture is proposed. The proposed AGC is composed of variable gain amplifier (VGA), comparator and charge pump, and the dB-linear gain is controlled by charge pump. The AGC was implemented in a 0.18um CMOS technology. The dynamic range of the VGA is more than 55dB, the bandwidth is 30MHz and the gain error lower than ±1.5dB over the full temperature and gain ranges. It is designed for GPS application and is fed from a single 1.8V power supply. The AGC power consumption is less than 5mW and area of the AGC is 700*450um2.     

基于边界扫描技术的FPGA延时故障检测

随着FPGA器件规模的不断提高,FPGA延时故障检测问题成为研究热点.文中对XC4006E的JTAG指令进行扩充,并修改相应的边界扫描电路,使其具备板级和芯片级延时故障检测能力.仿真结果显示,扩展后的JTAG指令不仅与原指令功能兼容,还可以有效地检测板级和芯片级延时故障.     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier(VGA) with novel DC offset calibration loop for direct-conversion receiver(DCR) is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier(PGA) can be converted to an analog controlled dB-linear VGA. An operational amplifier(OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation(DCOC) loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm~2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency(HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.