通用一体化测试平台设计

针对航天控制系统灵活性、复用性、可扩展性较差等问题,采用部分动态可重配置和软硬件协同设计等技术,设计了一种基于Microblaze软核的高带宽软件无线电(Software-defined Radio,SDR)通用一体化测试平台。该硬件平台由Kintex7 FPGA与集成式射频(Radio Frequency,RF)收发器AD9371组成,采用Microblaze软核进行功能开发,实现任务调度、功能配置和数据交互;通过Vivado实现测试平台逻辑功能开发,并将功能代码封装成FPGA IP(Intellectual Property)核;最终通过AD9371 RF收发器实现射频数据收发。测试结果表明,该通用一体化测试平台可进行高速率、高带宽数据传输。该平台具有通用性强、互联性强、易操作、易移植等特点,可广泛应用于工业、通信、军事、医疗、汽车、无人机、航天等领域。     

Embedded system design

In the past decade the main engine of electronic design automation has been the widespread application of ASICs (Application Specific Integrated Circuits). Present technology supports complete systems on a chip, most often used as so-called embedded systems in an increasing number of applications. Embedded systems pose new design challenges which we believe will be the driving forces of design automation in the years to come. These include the design of electronic systems hardware, embedded software and hardware / software codesign. This paper explores the novel technical challenges in embedded system design and presents experiences and results of the work in this area using the CASTLE system. CASTLE supports the design of complex embedded systems and the design of the required tools. It provides a central design representation, Verilog, VHDL and C/C++ frontends, Hardware generation in VHDL and BLIF, a retargetable compiler backend and several analysis and visualization tools. Two design examples, video compression and a diesel injection control, illustrate the presented concepts.     

基于UML的软硬件协同设计的模型分析方法

详细分析了Chonlameth Arpnikanondt提出的基于UML约束的嵌入式系统的软、硬件协同设计方法(CBC/UML),并指出了它运用于复杂的嵌入式系统设计时的不足.针对这些不足,扩展了约束的概念,提出了一套相应的改善方法.并利用中国科学院软件研究所研制智能电话机的例子具体阐述了该解决方法.     

Rapid Prototyping of Embedded Hardware/Software Systems

Prototyping of embedded hardware/software systems is important, because it shortens the path from specification to the final product. Prototypes play a major role in decision making, concept and design validation, feature and limit exploration, as well as design verification in every phase of the product development cycle, including product planning, requirement engineering, and product development. This overview discusses the motivation for building prototypes, provides the key areas for research and explains how prototypes can assist in product planning and throughout all steps of the engineering process. Special attention is given to prototyping in the industry to support the design and testing of multimodal and multifunctional embedded systems.     

一种基于SystemC的软硬件协同设计方法

随着集成电路工艺的飞速发展,传统的设计方法已不能满足设计高集成度的复杂数字系统的要求。软硬件协同设计成为嵌入式系统设计的新方法。SystemC是一种兼容C++的系统建模语言,它同时支持RTL级、行为级和系统级描述,使其成为软硬件协同设计平台的基础。     

一种纯滞后过程的串级双环状态反馈优化设计方法

纯滞后对象是一种很难控制的对象。文中采用串级双环状态反馈控制,使这种对象获得较理想的控制品质。系统的设计方法包括:采用数值逼近方法将对象拟合成有理多项式,并选择一种近乎理想的最优低通滤波器作为串级系统内外环的参考模型;根据串级内、外环不同结构分别采用开环和闭环校正,并引入状态观测器,大幅度地减少状态的检测数量;同时采用内外环系统的协调设计,拉开内外环回路的操作频率,有利于提高系统的鲁棒性。通过仿真实验,证实该方法相当有效。     

基于量子遗传算法的嵌入式系统软硬件划分算法

针对嵌入式系统软硬件协同设计中的软硬件划分问题，本文在改进了基于基本调度块图的软硬件划分模型的基础上，提出了一个基于量子遗传算法(QGA)的软硬件划分算法。通过采用自适应的适应度函数、惯性量子旋转角调整策略以及引入量子交叉操作，提高了算法的搜索效率，实验结果说明了该算法对解决软硬件划分问题的有效性。     

An Algorithm for Hardware/Software Partitioning Using Mixed Integer Linear Programming

One of the key problems in hardware/software codesign is hardware/software partitioning. This paper describes a new approach to hardware/software partitioning using integer programming (IP). The advantage of using IP is that optimal results are calculated for a chosen objective function. The partitioning approach works fully automatic and supports multi-processor systems, interfacing and hardware sharing. In contrast to other approaches where special estimators are used, we use compilation and synthesis tools for cost estimation. The increased time for calculating values for the cost metrics is compensated by an improved quality of the values. Therefore, fewer iteration steps for partitioning are needed. The paper presents an algorithm using integer programming for solving the hardware/software partitioning problem leading to promising results.     

Multi-layer bus minimization for SoC

The deployment of multiple processing elements such as a microprocessor or a Digital Signal Processor in embedded systems often results in significant communication overheads. The challenge lies in resolving the communication cost minimization problem, while simultaneously satisfying the timing constraints of job executions. In this paper, we explore bus-layer minimization problems by first identifying factors that contribute to the NP-hardness of these problems. Existing proposed algorithms and NP-hard problems are then identified and elucidated. A simulated annealing algorithm is proposed and compared with heuristics-based algorithms to provide further insights for system designers. Lastly, a series of extensive simulations is carried out and a case study is presented to show comparisons among different approaches and workloads.